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(parent: aca5f01) | patch
fsl-ddr: update the bit mask for DDR3 controller
authorDave Liu <daveliu@freescale.com>
Fri, 21 Nov 2008 08:31:22 +0000 (16:31 +0800)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Fri, 23 Jan 2009 23:03:13 +0000 (17:03 -0600)
commit80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106
tree272a979e6e9ed0ae0ab583068657c33793b4355ctree | snapshot
parentaca5f018a8386b85469482ed9867e3e29a2437d0commit | diff
fsl-ddr: update the bit mask for DDR3 controller

According to the latest 8572 UM, the DDR3 controller
is expanding the bit mask, and we use the extend ACTTOPRE
mode when tRAS more than 19 MCLK.

Signed-off-by: Dave Liu <daveliu@freescale.com>
cpu/mpc8xxx/ddr/ctrl_regs.c diff | blob | history
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