ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access
authorThor Thayer <thor.thayer@linux.intel.com>
Fri, 6 Dec 2019 19:47:32 +0000 (13:47 -0600)
committerMarek Vasut <marex@denx.de>
Tue, 7 Jan 2020 13:38:34 +0000 (14:38 +0100)
commit8097aee3abc3b773aceea01f756a38b34b274e1e
treed1da575ae9397760133c6e47d9333540e4575dec
parent62079b2211e113f8ee395025d1213f91e1da219e
ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access

The ECC registers in the SDRAM HMC Adapter should always
be accessible (both when ECC is enabled and disabled).
Currently, the registers are accessible only when ECC is enabled.

The ECC Enabled bit is used to determine the status of
ECC by later OSes so always allow access.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
drivers/ddr/altera/sdram_agilex.c
drivers/ddr/altera/sdram_s10.c