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(parent: 3f21501) | patch
imx: mx6q_4x_mt41j128.cfg: Setup CCM_CCOSR register
authorFabio Estevam <fabio.estevam@freescale.com>
Wed, 17 Apr 2013 08:33:26 +0000 (08:33 +0000)
committerStefano Babic <sbabic@denx.de>
Thu, 25 Apr 2013 19:14:19 +0000 (21:14 +0200)
commit7a56f1791d84bb0fbd4e40bb6731915cc5ff6251
treec00a27603fa5819eee8b7f1df64b750cd404d3c2tree | snapshot
parent3f215011142a7c3ed6e38f2712b8e875b8dcfd0fcommit | diff
imx: mx6q_4x_mt41j128.cfg: Setup CCM_CCOSR register

Setup CCM_CCOSR register to provide a CKO1 clock frequency of 16.5 MHz.

CKO1 drives sgtl5000 codec clock on mx6qsabrelite and doing this setup in the
bootloader will allow us to remove a lot of code in arch/arm/mach-imx/mach-imx6q.c
from the mainline kernel.

mx6q_4x_mt41j128.cfg is also used by mx6qsabresd, and it is safe to use it for
this board as well.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg diff | blob | history
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