phy: marvell: mux: Support nontrivial node order in selector register
authorMarek BehĂșn <marek.behun@nic.cz>
Tue, 24 Apr 2018 15:21:21 +0000 (17:21 +0200)
committerStefan Roese <sr@denx.de>
Mon, 14 May 2018 08:00:15 +0000 (10:00 +0200)
commit7586ac2b49dd3046868354201ab6a208c3a5b82c
treef22015dffc89ac087264c5fed6fda8c591e437e5
parent7d7f22fbd30ec925b278275bd8b950837d6d3c7e
phy: marvell: mux: Support nontrivial node order in selector register

Currently comphy_mux supports only trivial order of nodes in pin
selector register, that is lane N on position N*bitcount.

Add support for nontrivial order, with map stored in device tree
property mux-lane-order.

This is needed for Armada 37xx.

As far as I know, there is no driver for Armada 37xx comphy in the
kernel. When such a driver comes, this will need to be rewritten to
support the device tree bindings from the kernel.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
drivers/phy/marvell/comphy.h
drivers/phy/marvell/comphy_core.c
drivers/phy/marvell/comphy_mux.c