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mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue
authorYe Li <ye.li@nxp.com>
Mon, 7 Jan 2019 03:18:06 +0000 (03:18 +0000)
committerPeng Fan <peng.fan@nxp.com>
Fri, 3 May 2019 12:03:41 +0000 (20:03 +0800)
commit72a89e0da5ac6a4ab929b15a2b656f04f50767f6
tree311a4c938f6fb4afd4623f8f4179aa75757471f0tree | snapshot
parentb4ee6daad7a2604ca9466b2ba48de86cc27d381fcommit | diff
mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue

When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode,
the output clock rate is half of the internal clock rate.

This patch set the DDR_EN bit first for DDR mode, hardware divide
the usdhc clock automatically, then follow the original sdr clock
setting method.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
drivers/mmc/fsl_esdhc.c diff | blob | history
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