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(parent: 0e4c1dd) | patch
arm: zynq: Add support for DLC20 board
authorMichal Simek <michal.simek@xilinx.com>
Thu, 13 Sep 2018 06:44:02 +0000 (08:44 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 16 Oct 2018 12:58:45 +0000 (14:58 +0200)
commit6bfe3fffac1bb15b95f9e047224ac57441e46b7e
treeb8b9281ae1e35f3ada1e0694e34ae9b3c517a661tree | snapshot
parent0e4c1dd29026ee76b2ae8fb27a99366ac7d0b289commit | diff
arm: zynq: Add support for DLC20 board

Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).

Boards have mix of Winbond/ST QSPIs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/dts/Makefile diff | blob | history
arch/arm/dts/zynq-dlc20-rev1.0.dts [new file with mode: 0644] blob
board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c [new file with mode: 0644] blob
configs/zynq_dlc20_rev1_0_defconfig [new file with mode: 0644] blob
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