Fix DDR2 setup on AR934x and QCA95xx

Fix DDR2 setup on AR934x and QCA95xx

Instead of set/unset a SEL_18 bit field in DDR_CTL_CONFIG register,
without touching values of rest of the fields, the code was writing
value 0x40 (bit 6 set) into register (and clearing other fields).

This bug was causing problems with DDR2 initialization at least on
AR934{1,2} with DDR2 memory type.