clk: sunxi: Add Allwinner A10/A20 CLK driver
authorJagan Teki <jagan@amarulasolutions.com>
Thu, 2 Aug 2018 11:22:37 +0000 (16:52 +0530)
committerJagan Teki <jagan@amarulasolutions.com>
Fri, 18 Jan 2019 16:49:08 +0000 (22:19 +0530)
commit6590bd8c47b47ae97ac43efd17c8a0e2f5ddb855
tree66b1e08400493cb4d5ff24b5151efb5104d078a1
parente945816efbd3541f4a4e877e13221768f0b9f775
clk: sunxi: Add Allwinner A10/A20 CLK driver

Add initial clock driver for Allwinner A10/A20.

- Implement USB ahb and USB clocks via ccu_clk_gate table
  for A10/A20, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10/A20,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
drivers/clk/sunxi/Kconfig
drivers/clk/sunxi/Makefile
drivers/clk/sunxi/clk_a10.c [new file with mode: 0644]