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ARM: dts: socfpga: Adjust NAND register layout on Arria10
authorMarek Vasut <marex@denx.de>
Mon, 7 May 2018 20:22:26 +0000 (22:22 +0200)
committerMarek Vasut <marex@denx.de>
Tue, 24 Jul 2018 22:13:32 +0000 (00:13 +0200)
commit64eeb1585428b71e29022e22d1aae86b65b9e052
treee81ae5caa33279729457ea7ab0e93ff6c7ef5417tree | snapshot
parent42f4b83b52735d698bf3f3de2665bf6d42db9f1ccommit | diff
ARM: dts: socfpga: Adjust NAND register layout on Arria10

Adjust the NAND register size on Arria10 to reflect reality.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
arch/arm/dts/socfpga_arria10.dtsi diff | blob | history
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