x86: Enable mrc cache for bayleybay and minnowmax
authorBin Meng <bmeng.cn@gmail.com>
Mon, 12 Oct 2015 04:37:44 +0000 (21:37 -0700)
committerSimon Glass <sjg@chromium.org>
Wed, 21 Oct 2015 13:46:27 +0000 (07:46 -0600)
commit638a05894169b07ea8f6d21b6925ca353ea6ebb7
tree68308063e00f4b803a07b9f55d56b2973edc2c7b
parent8b185041a9f4c30dc5edb1e04c0834e931b8633f
x86: Enable mrc cache for bayleybay and minnowmax

Now that we have added MRC cache for Intel FSP and BayTrail codes,
enable it for all BayTrail boards (Bayley Bay and Minnow Max).

Note it turns out that FSP for Intel Atom E6xx does not produce
the HOB for NV storage, so we don't have such functionality on
Intel Crown Bay board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
arch/x86/dts/bayleybay.dts
arch/x86/dts/minnowmax.dts
configs/bayleybay_defconfig
configs/minnowmax_defconfig
doc/README.x86