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EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0
authorRajeshwari Shinde <rajeshwari.s@samsung.com>
Tue, 3 Jul 2012 20:02:57 +0000 (20:02 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 1 Sep 2012 12:58:23 +0000 (14:58 +0200)
commit6071bcaec1cbbdd2679f9abdd36dfe16114bc315
tree142468c8d25f58f06e357b947298461c28a04dfatree | snapshot
parent87f2e079dbbe517003bd2c3910ae2512ab27a6f5commit | diff
EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0

MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
arch/arm/cpu/armv7/exynos/clock.c diff | blob | history
arch/arm/include/asm/arch-exynos/clock.h diff | blob | history
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