board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings
authorSchuyler Patton <spatton@ti.com>
Fri, 8 Apr 2016 21:53:44 +0000 (16:53 -0500)
committerTom Rini <trini@konsulko.com>
Mon, 18 Apr 2016 21:11:32 +0000 (17:11 -0400)
commit5f405e7fa0c4baf4cc57a82d2fcddb86789cfaed
tree3c2caa16843be6bba3e92e2efa7b7e6d3146f326
parent7e52e11f3537809e48a6e337c392a1289a692061
board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings

Update EMIF data based on recommendations from the now standard TI
EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB
data sheet

Update T_RRD from 5 to 6 based on AM57xx TRM -
Minimum number of DDR cycles from activate to ativate for a different
bank, minus 1.

Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR
clocks cycles for which SDRAM must remain in self refresh, minus 1.

Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
board/ti/am57xx/board.c