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board/t1040qds: Relax IFC FPGA timings
authorPrabhakar Kushwaha <prabhakar@freescale.com>
Thu, 12 Dec 2013 06:39:01 +0000 (12:09 +0530)
committerYork Sun <yorksun@freescale.com>
Thu, 2 Jan 2014 22:10:13 +0000 (14:10 -0800)
commit562de1d6da5bdc1789bd258d464d6ca57571861d
tree84ada120ab90055522b69a080817f2c5bbb13bc4tree | snapshot
parentfbe76ae4e3bacd5183294488947ec148df28d55bcommit | diff
board/t1040qds: Relax IFC FPGA timings

Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion)
is 0 i.e. 0 ns hold time on writes. This may not work on higher clock
freqencies.

So, Increase TCH as 0x8 i.e. 8 ip_clk.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
include/configs/T1040QDS.h diff | blob | history
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