net: phy: mv88e61xx: add CPU port parameter init for 88E6071
authorAnatolij Gustschin <agust@denx.de>
Sat, 26 Oct 2019 23:14:38 +0000 (01:14 +0200)
committerJoe Hershberger <joe.hershberger@ni.com>
Mon, 9 Dec 2019 15:47:42 +0000 (09:47 -0600)
commit4aa05f6cf3e893ba2394d81e586400872e3303c1
tree45c3236d1f39db0f559c87f45f2d9ff447964a71
parentf41a722baa9fab4eb6843eca51f0318ad104f145
net: phy: mv88e61xx: add CPU port parameter init for 88E6071

On 88E6071 chip the port status register bit field offsets
for duplex and link bits differ. Extend the driver to use
88E6071 specific offset values. The width of bit fields for
speed status differ, too. Adapt for proper port speed
detection on 88E6071.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
drivers/net/phy/mv88e61xx.c