drivers/crypto/fsl: fix endianness issue in RNG
authorAneesh Bansal <aneesh.bansal@freescale.com>
Tue, 8 Dec 2015 08:24:30 +0000 (13:54 +0530)
committerYork Sun <yorksun@freescale.com>
Tue, 15 Dec 2015 00:57:35 +0000 (08:57 +0800)
commit3a4800a5968f689788d70f7decb000a3d3e1a2f4
tree45e595cb658089cc2776fa3c7e99be7e04031086
parent9711f52806655bcfa28fe5594b91fed430beb72e
drivers/crypto/fsl: fix endianness issue in RNG

For Setting and clearing the bits in SEC Block registers
sec_clrbits32() and sec_setbits32() are used which work as
per endianness of CAAM block.
So these must be used with SEC register address as argument.
If the value is read in a local variable, then the functions
will not behave correctly where endianness of CAAM and core is
different.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
CC: Alex Porosanu <alexandru.porosanu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
drivers/crypto/fsl/jr.c