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armv8/ls2080ardb: Update DDR settings for four chip-select case
authorYork Sun <yorksun@freescale.com>
Wed, 4 Nov 2015 18:03:23 +0000 (10:03 -0800)
committerYork Sun <yorksun@freescale.com>
Mon, 14 Dec 2015 02:27:28 +0000 (18:27 -0800)
commit3901978d42b7008b13e7e9b67bea12a51cc5847b
treedf251b3cd312040e5108e8acdd9fa5cc2750acectree | snapshot
parentc4243ac9e2713897a63dcdc3a96bf088fdb49866commit | diff
armv8/ls2080ardb: Update DDR settings for four chip-select case

When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.

Signed-off-by: York Sun <yorksun@freescale.com>
board/freescale/ls2080ardb/ddr.c diff | blob | history
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