MIPS: Split I & D cache line size config
authorPaul Burton <paul.burton@imgtec.com>
Fri, 27 May 2016 13:28:05 +0000 (14:28 +0100)
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tue, 31 May 2016 07:44:24 +0000 (09:44 +0200)
commit372286217f050bfd57695001d59f618c52822f40
treee2d926d936e6d65f2a229b19a347435f9f1d8d56
parentace3be4f15875d74344336b9754c14274f940969
MIPS: Split I & D cache line size config

Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
12 files changed:
arch/mips/Kconfig
arch/mips/include/asm/cache.h
arch/mips/lib/cache.c
arch/mips/lib/cache_init.S
board/dbau1x00/Kconfig
board/micronas/vct/Kconfig
board/pb1x00/Kconfig
board/qca/ap121/Kconfig
board/qca/ap143/Kconfig
board/qemu-mips/Kconfig
board/tplink/wdr4300/Kconfig
include/configs/pic32mzdask.h