Add new, common setup code for QC/A WiSoC DDR controllers

Add new, common setup code for QC/A WiSoC DDR controllers

In old code, based on Qualcomm/Atheros (Q)SDK, most of the
DDR controller related registers where setup with static
values, based on selected PLL/clocks configuration or
chosen board type.

New setup code is universal and configures DDR controller
based on real hardware state (clocks, memory type).

For now, the code doesn't support SDRAM memory type,
as I don't have access to any QC/A based platform with
such type of memory chip. But it seems, that newer QC/A
WiSoCs don't support it (excluding QCA953x v1?) anyway.

New code contains also fixed DQS delay tap controller tune
for AR93xx WiSoCs, which for now is used only for AR933x,
as it turned out that DDR BITS is available also on AR934x.

In old code, tune routine starts with some hardcoded values,
which leads to an assumption that this starting value is
inside working tap range. As it turned out after some tests,
this assumption is wrong and on some real hardware platforms
gives wrong delay tap values, outside correct/working range.

New code was tested on many different QC/A platforms, but
will need changes and fixes in future, mostly because of
missing (at the moment) descriptions of DDR BIST registers.