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x86: ivybridge: Add microcode blobs for all the steppings
authorBin Meng <bmeng.cn@gmail.com>
Fri, 11 Dec 2015 10:55:47 +0000 (02:55 -0800)
committerBin Meng <bmeng.cn@gmail.com>
Wed, 13 Jan 2016 04:20:15 +0000 (12:20 +0800)
commit33fb6c0100de6dbc79d0237418941cc40e94b16d
tree47cc287d70dcfcdee7671e4017078c73485bf0ectree | snapshot
parentaefba6f1b5681f124b5dce4908219eb6374533c9commit | diff
x86: ivybridge: Add microcode blobs for all the steppings

This adds microcode blobs created from Intel FSP package for the
Chief River platform. They are for all the Ivy Bridge steppings:
306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
306a9 which is already in the U-Boot tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
arch/x86/dts/microcode/m12306a2_00000008.dtsi [new file with mode: 0644] blob
arch/x86/dts/microcode/m12306a4_00000007.dtsi [new file with mode: 0644] blob
arch/x86/dts/microcode/m12306a5_00000007.dtsi [new file with mode: 0644] blob
arch/x86/dts/microcode/m12306a8_00000010.dtsi [new file with mode: 0644] blob
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