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(parent: 61927d2) | patch
clk: meson: fix clk81 divider calculation
authorJerome Brunet <jbrunet@baylibre.com>
Tue, 13 Nov 2018 10:38:38 +0000 (11:38 +0100)
committerTom Rini <trini@konsulko.com>
Tue, 20 Nov 2018 17:35:35 +0000 (12:35 -0500)
commit2fa77bd12533e29e1b0f1742f66f258700715d52
treebdc9478627942cc191eab3f360ce37acd5a82f56tree | snapshot
parent61927d286d2a4f4fd975967655590e8a59588533commit | diff
clk: meson: fix clk81 divider calculation

clk81 divider is 0 based (meaning that 0 value in the register means
divide by 1). Fix clk81 rate calculation for this.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
drivers/clk/clk_meson.c diff | blob | history
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