ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC
authorYork Sun <yorksun@freescale.com>
Mon, 23 Jun 2014 22:15:54 +0000 (15:15 -0700)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Thu, 3 Jul 2014 06:40:51 +0000 (08:40 +0200)
commit2f78eae5064728d6cd907148cfeaf8ba3e63b0ef
tree80b5d23e3c6d46424909954cbc9504288e8f7156
parent22932ffc03e521130cfd33cae1fc2531eb42604a
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC

Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
17 files changed:
arch/arm/cpu/armv8/cache_v8.c
arch/arm/cpu/armv8/fsl-lsch3/Makefile [new file with mode: 0644]
arch/arm/cpu/armv8/fsl-lsch3/README [new file with mode: 0644]
arch/arm/cpu/armv8/fsl-lsch3/cpu.c [new file with mode: 0644]
arch/arm/cpu/armv8/fsl-lsch3/cpu.h [new file with mode: 0644]
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S [new file with mode: 0644]
arch/arm/cpu/armv8/fsl-lsch3/speed.c [new file with mode: 0644]
arch/arm/cpu/armv8/fsl-lsch3/speed.h [new file with mode: 0644]
arch/arm/include/asm/arch-fsl-lsch3/clock.h [new file with mode: 0644]
arch/arm/include/asm/arch-fsl-lsch3/config.h [new file with mode: 0644]
arch/arm/include/asm/arch-fsl-lsch3/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h [new file with mode: 0644]
arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h [new file with mode: 0644]
arch/arm/include/asm/config.h
arch/arm/include/asm/system.h
drivers/i2c/mxc_i2c.c
include/common.h