rockchip: rk3288: Fix pinctrl for GPIO bank 0
authorJohn Keeping <john@metanate.com>
Mon, 25 Jul 2016 09:02:05 +0000 (10:02 +0100)
committerSimon Glass <sjg@chromium.org>
Sun, 31 Jul 2016 13:24:20 +0000 (07:24 -0600)
commit2b51784aef46523ed70916b09de125bc5fbefa25
tree299422c99bc7a934e2064b6f0d5f3a1e679d695b
parent633fdab0cb95a274a17108cd14ceafab1d4b7430
rockchip: rk3288: Fix pinctrl for GPIO bank 0

Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers
rather than the GRF registers.  In the GRF the top half of the register
is used as a mask so that some bits can be updated without affecting the
others, but in the PMU this feature is not provided and the top half of
the register is reserved.

Take the same approach as the Linux driver to update the value via
read-modify-write but setting the mask for only the bits that have
changed.  The PMU registers ignore the top 16 bits so this works for
both GRF and PMU iomux registers.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
drivers/pinctrl/rockchip/pinctrl_rk3288.c