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arm64: versal: fpga: Add PL bit stream load support
authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Mon, 5 Aug 2019 10:24:59 +0000 (15:54 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 8 Oct 2019 07:11:14 +0000 (09:11 +0200)
commit26e054c943a7348904a8b432fc9a85185b0861c7
treee9fe6b1ff6f4f9e1907df5390b59bf07fe983766tree | snapshot
parent13210cd951046e828ecf3463f0087acbfb4f185ecommit | diff
arm64: versal: fpga: Add PL bit stream load support

This patch adds PL bitstream load support for Versal platform. The PL
bitstream is loaded by making an SMC to ATF which in turn communicates
with platform firmware which configures and loads PL bitstream on to PL.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
board/xilinx/versal/board.c diff | blob | history
drivers/fpga/Kconfig diff | blob | history
drivers/fpga/Makefile diff | blob | history
drivers/fpga/versalpl.c [new file with mode: 0644] blob
drivers/fpga/xilinx.c diff | blob | history
include/versalpl.h [new file with mode: 0644] blob
include/xilinx.h diff | blob | history
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