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(parent: e4d2318) | patch
net: zynq: Fix mdc clock division setting for 100Mbit/s
authorMichal Simek <michal.simek@xilinx.com>
Tue, 8 Sep 2015 14:55:42 +0000 (16:55 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Thu, 19 Nov 2015 13:03:05 +0000 (14:03 +0100)
commit242b15476c94752494670a3e419e639d2df08dfd
tree90eb87ea90995ce5a4f302a22178381a8e2601a1tree | snapshot
parente4d2318adbcff084dbbed2f84e4a51da09a1b21bcommit | diff
net: zynq: Fix mdc clock division setting for 100Mbit/s

Using set and clear macro is incorrect because it is not overwritting
origin mdc clock division setup.
For example origin setup is 8(0b001) and new setup is 64(0b100) which
means 0b101 is setup which is 96 divider.
Using writel to rewrite all setting like for 1000Mbit/s case.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
drivers/net/zynq_gem.c diff | blob | history
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