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(parent: 80ee3ce) | patch
fsl-ddr: clean up the ddr code for DDR3 controller
authorDave Liu <daveliu@freescale.com>
Fri, 21 Nov 2008 08:31:29 +0000 (16:31 +0800)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Fri, 23 Jan 2009 23:03:13 +0000 (17:03 -0600)
commit22ff3d01348e0a2dc369b7efcbac30e4ce86d178
treee3ed66edb226e004cc85cdc4d4a966c55ce4f141tree | snapshot
parent80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106commit | diff
fsl-ddr: clean up the ddr code for DDR3 controller

- The DDR3 controller is expanding the bits for timing config
- Add the DDR3 32-bit bus mode support

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
cpu/mpc8xxx/ddr/ctrl_regs.c diff | blob | history
include/asm-ppc/fsl_ddr_sdram.h diff | blob | history
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