Add initial version of new QC/A SPI FLASH driver

Add initial version of new QC/A SPI FLASH driver

Instead of using so called bit banging/blasting mode, as the old one driver from Atheros SDK does, this driver utilizes SPI shift registers.
With this approach, we need to only setup one register and let the built-in SPI controller do the rest.

SPI shift registers and how they work exactly are not described very well in QC/A WiSoCs datasheets, so som things had to be tested in practice.

This driver has been already successfully tested on all supported platforms, including:
- Atheros AR933x (SPI shift registers are not mentioned in its datasheet!)
- Atheros AR9341/4
- Qualcomm Atheros QCA953x

Tests on scope showed that with this driver, clock for SPI is the same as the one set in SPI_CONTROL register (depends on platform, between 25 and 30 MHz).
With old driver, clock was around 4-6 MHz, which means that new driver may drastically increase SPI operations speed.

In practical tests, for operations like sector erase, time needed by chip to finish the operation, is more significant, so there is no difference at all.
Comparison for other operations, like page program, has not been done yet.