fsl/pci: Set CFG_READY for PCIe v3.0 and later
authorMinghuan Lian <Minghuan.Lian@freescale.com>
Fri, 27 Mar 2015 05:24:39 +0000 (13:24 +0800)
committerYork Sun <yorksun@freescale.com>
Mon, 4 May 2015 16:24:23 +0000 (09:24 -0700)
commit1d0b59a9b049443397f484ad03b88c6314bc7ebb
tree3aa8fc04de6bfd03c81ee07ee443bec9be07995d
parent5066e62847bddf6030262ade2aa3e7bcdc930037
fsl/pci: Set CFG_READY for PCIe v3.0 and later

Freescale PCIe controllers v3.0 and later need to set bit
CFG_READY to allow all inbound configuration transactions
to be processed normally when in EP mode. However, bit
CFG_READY has been moved from PCIe configuration space to
CCSR PCIe configuration register comparing previous version.
The patch is to set this bit according to PCIe version.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/powerpc/include/asm/fsl_pci.h
drivers/pci/fsl_pci_init.c