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(parent: 1a4bf17) | patch
arm: zynq: zybo z7: fix SPL uart init bitrate
authorMilan Obuch <u-boot@dino.sk>
Mon, 20 Jan 2020 01:32:19 +0000 (22:32 -0300)
committerMichal Simek <michal.simek@xilinx.com>
Fri, 28 Feb 2020 11:04:10 +0000 (12:04 +0100)
commit1bf9e01b8f82c442029607ab953c6a0d099c7d68
tree41c6a8cdedd6813728a358223c3cbdcc1364e8betree | snapshot
parent1a4bf17b0298257b35611453e44f53c72a55f8a7commit | diff
arm: zynq: zybo z7: fix SPL uart init bitrate

The board uses 100 MHz clock for UART bitrate generator,
but is configured as 50 MHz on defconfig.

This produces wrong console output.
The first message, "Debug uart enabled" is received as:
"������b"

Fix the issue by configuring the correct clock for the
UART baudrate generator

Signed-off-by: Milan Obuch <u-boot@dino.sk>
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
configs/zynq_zybo_z7_defconfig diff | blob | history
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