x86: Implement a cache for Memory Reference Code parameters
authorSimon Glass <sjg@chromium.org>
Tue, 20 Jan 2015 05:16:14 +0000 (22:16 -0700)
committerSimon Glass <sjg@chromium.org>
Sat, 24 Jan 2015 13:13:45 +0000 (06:13 -0700)
commit191c008a2155f99fc6476539878640b4032a457b
tree36823854ae5d3de1b03646f7d8230df51a62743e
parenta9aff2f46a7f7d29a662531dbc181773f16a606d
x86: Implement a cache for Memory Reference Code parameters

The memory reference code takes a very long time to 'train' its SDRAM
interface, around half a second. To avoid this delay on every boot we can
store the parameters from the last training sessions to speed up the next.

Add an implementation of this, storing the training data in CMOS RAM and
SPI flash.

Signed-off-by: Simon Glass <sjg@chromium.org>
arch/x86/cpu/ivybridge/Makefile
arch/x86/cpu/ivybridge/mrccache.c [new file with mode: 0644]
arch/x86/cpu/ivybridge/sdram.c
arch/x86/include/asm/arch-ivybridge/mrccache.h [new file with mode: 0644]
arch/x86/include/asm/global_data.h