clk: clk_stm32f7: fix PLL clock division factor
authorPatrice Chotard <patrice.chotard@st.com>
Thu, 26 Oct 2017 11:23:19 +0000 (13:23 +0200)
committerTom Rini <trini@konsulko.com>
Fri, 17 Nov 2017 12:44:13 +0000 (07:44 -0500)
commit1543bf794f4cf863b4c70eb9debba5fc1d2ebd6b
treee274e317b778b67e276832726a2c5de4284c8240
parent5829fe2d59d8c088dadc43dedb36a657d791970c
clk: clk_stm32f7: fix PLL clock division factor

Fix clock division factor initialization for RCC_PLLCFGR
registers.

PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared,
it's a forbidden value. So update RCC_PLLCFGR using
clrsetbits_le32() to set only necessary bits fields.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
drivers/clk/clk_stm32f7.c