arm: socfpga: Sync Cyclone V DK PLL configuration
authorMarek Vasut <marex@denx.de>
Tue, 30 Dec 2014 18:41:17 +0000 (19:41 +0100)
committerMarek Vasut <marex@denx.de>
Wed, 4 Mar 2015 22:07:04 +0000 (23:07 +0100)
commit0d13a0051b22c95822703e64d0046bbf3b36b13b
treed3cf646e8bbd319ec86624759630704638f18048
parenta2d96abe398b160b8bbed04c86f00df5e3d4fb98
arm: socfpga: Sync Cyclone V DK PLL configuration

Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

NOTE: This change is useless until we get proper SPL support, at
      which point this will likely need further rework.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
board/altera/socfpga/pll_config.h