X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=target%2Flinux%2Flayerscape%2Fpatches-4.9%2F804-crypto-support-layerscape.patch;h=2598cdedbb2d720f6055520e7682cf95230796f3;hb=9e1530b2a35e051664ed243efd1eac942883494a;hp=6b6104dd05b216e1c2e64efecb04653ba153e6b3;hpb=ce6311d2836408f8e79596d1c8d4daf85e94a672;p=oweals%2Fopenwrt.git diff --git a/target/linux/layerscape/patches-4.9/804-crypto-support-layerscape.patch b/target/linux/layerscape/patches-4.9/804-crypto-support-layerscape.patch index 6b6104dd05..2598cdedbb 100644 --- a/target/linux/layerscape/patches-4.9/804-crypto-support-layerscape.patch +++ b/target/linux/layerscape/patches-4.9/804-crypto-support-layerscape.patch @@ -1,12 +1,12 @@ -From 9c9579d76ccd6e738ab98c9b4c73c168912cdb8a Mon Sep 17 00:00:00 2001 +From a3310d64d7cb1ba0f9279e77d21f13a75fa66ab5 Mon Sep 17 00:00:00 2001 From: Yangbo Lu -Date: Wed, 27 Sep 2017 15:02:01 +0800 -Subject: [PATCH] crypto: support layerscape +Date: Wed, 17 Jan 2018 15:29:23 +0800 +Subject: [PATCH 16/30] crypto: support layerscape MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit -This is a integrated patch for layerscape sec support. +This is an integrated patch for layerscape sec support. Signed-off-by: Radu Alexe Signed-off-by: Fabio Estevam @@ -36,39 +36,41 @@ Signed-off-by: Yangbo Lu crypto/crypto_user.c | 19 + crypto/scompress.c | 356 ++ crypto/tcrypt.c | 17 +- - crypto/testmgr.c | 1701 ++++---- - crypto/testmgr.h | 1125 +++--- + crypto/testmgr.c | 1708 +++--- + crypto/testmgr.h | 1125 ++-- crypto/tls.c | 607 +++ - drivers/crypto/caam/Kconfig | 72 +- - drivers/crypto/caam/Makefile | 15 +- - drivers/crypto/caam/caamalg.c | 2125 +++------- - drivers/crypto/caam/caamalg_desc.c | 1913 +++++++++ + drivers/crypto/caam/Kconfig | 77 +- + drivers/crypto/caam/Makefile | 16 +- + drivers/crypto/caam/caamalg.c | 2171 ++------ + drivers/crypto/caam/caamalg_desc.c | 1961 +++++++ drivers/crypto/caam/caamalg_desc.h | 127 + - drivers/crypto/caam/caamalg_qi.c | 2877 +++++++++++++ - drivers/crypto/caam/caamalg_qi2.c | 4428 +++++++++++++++++++++ - drivers/crypto/caam/caamalg_qi2.h | 265 ++ - drivers/crypto/caam/caamhash.c | 521 +-- - drivers/crypto/caam/caampkc.c | 471 ++- + drivers/crypto/caam/caamalg_qi.c | 2929 ++++++++++ + drivers/crypto/caam/caamalg_qi2.c | 5920 +++++++++++++++++++++ + drivers/crypto/caam/caamalg_qi2.h | 281 + + drivers/crypto/caam/caamhash.c | 550 +- + drivers/crypto/caam/caamhash_desc.c | 108 + + drivers/crypto/caam/caamhash_desc.h | 49 + + drivers/crypto/caam/caampkc.c | 471 +- drivers/crypto/caam/caampkc.h | 58 + drivers/crypto/caam/caamrng.c | 16 +- drivers/crypto/caam/compat.h | 1 + - drivers/crypto/caam/ctrl.c | 356 +- + drivers/crypto/caam/ctrl.c | 358 +- drivers/crypto/caam/ctrl.h | 2 + - drivers/crypto/caam/desc.h | 55 +- - drivers/crypto/caam/desc_constr.h | 139 +- - drivers/crypto/caam/dpseci.c | 859 ++++ + drivers/crypto/caam/desc.h | 84 +- + drivers/crypto/caam/desc_constr.h | 180 +- + drivers/crypto/caam/dpseci.c | 859 +++ drivers/crypto/caam/dpseci.h | 395 ++ - drivers/crypto/caam/dpseci_cmd.h | 261 ++ + drivers/crypto/caam/dpseci_cmd.h | 261 + drivers/crypto/caam/error.c | 127 +- drivers/crypto/caam/error.h | 10 +- drivers/crypto/caam/intern.h | 31 +- - drivers/crypto/caam/jr.c | 97 +- + drivers/crypto/caam/jr.c | 72 +- drivers/crypto/caam/jr.h | 2 + drivers/crypto/caam/key_gen.c | 32 +- drivers/crypto/caam/key_gen.h | 36 +- drivers/crypto/caam/pdb.h | 62 + drivers/crypto/caam/pkc_desc.c | 36 + - drivers/crypto/caam/qi.c | 797 ++++ + drivers/crypto/caam/qi.c | 797 +++ drivers/crypto/caam/qi.h | 204 + drivers/crypto/caam/regs.h | 63 +- drivers/crypto/caam/sg_sw_qm.h | 126 + @@ -77,14 +79,14 @@ Signed-off-by: Yangbo Lu drivers/net/wireless/rsi/rsi_91x_usb.c | 2 +- drivers/staging/wilc1000/linux_wlan.c | 2 +- drivers/staging/wilc1000/wilc_wfi_cfgoperations.c | 2 +- - include/crypto/acompress.h | 269 ++ + include/crypto/acompress.h | 269 + include/crypto/internal/acompress.h | 81 + include/crypto/internal/scompress.h | 136 + include/linux/crypto.h | 3 + include/uapi/linux/cryptouser.h | 5 + scripts/spelling.txt | 3 + sound/soc/amd/acp-pcm-dma.c | 2 +- - 55 files changed, 17310 insertions(+), 3955 deletions(-) + 57 files changed, 19177 insertions(+), 3988 deletions(-) create mode 100644 crypto/acompress.c create mode 100644 crypto/scompress.c create mode 100644 crypto/tls.c @@ -93,6 +95,8 @@ Signed-off-by: Yangbo Lu create mode 100644 drivers/crypto/caam/caamalg_qi.c create mode 100644 drivers/crypto/caam/caamalg_qi2.c create mode 100644 drivers/crypto/caam/caamalg_qi2.h + create mode 100644 drivers/crypto/caam/caamhash_desc.c + create mode 100644 drivers/crypto/caam/caamhash_desc.h create mode 100644 drivers/crypto/caam/dpseci.c create mode 100644 drivers/crypto/caam/dpseci.h create mode 100644 drivers/crypto/caam/dpseci_cmd.h @@ -104,8 +108,6 @@ Signed-off-by: Yangbo Lu create mode 100644 include/crypto/internal/acompress.h create mode 100644 include/crypto/internal/scompress.h -diff --git a/crypto/Kconfig b/crypto/Kconfig -index 17be110a..00e145e2 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -102,6 +102,15 @@ config CRYPTO_KPP @@ -159,8 +161,6 @@ index 17be110a..00e145e2 100644 comment "Block modes" config CRYPTO_CBC -diff --git a/crypto/Makefile b/crypto/Makefile -index 9e52b3c5..936d2b73 100644 --- a/crypto/Makefile +++ b/crypto/Makefile @@ -51,6 +51,9 @@ rsa_generic-y += rsa_helper.o @@ -173,7 +173,7 @@ index 9e52b3c5..936d2b73 100644 cryptomgr-y := algboss.o testmgr.o obj-$(CONFIG_CRYPTO_MANAGER2) += cryptomgr.o -@@ -115,6 +118,7 @@ obj-$(CONFIG_CRYPTO_CRC32C) += crc32c_generic.o +@@ -115,6 +118,7 @@ obj-$(CONFIG_CRYPTO_CRC32C) += crc32c_ge obj-$(CONFIG_CRYPTO_CRC32) += crc32_generic.o obj-$(CONFIG_CRYPTO_CRCT10DIF) += crct10dif_common.o crct10dif_generic.o obj-$(CONFIG_CRYPTO_AUTHENC) += authenc.o authencesn.o @@ -181,9 +181,6 @@ index 9e52b3c5..936d2b73 100644 obj-$(CONFIG_CRYPTO_LZO) += lzo.o obj-$(CONFIG_CRYPTO_LZ4) += lz4.o obj-$(CONFIG_CRYPTO_LZ4HC) += lz4hc.o -diff --git a/crypto/acompress.c b/crypto/acompress.c -new file mode 100644 -index 00000000..887783d8 --- /dev/null +++ b/crypto/acompress.c @@ -0,0 +1,169 @@ @@ -356,11 +353,9 @@ index 00000000..887783d8 + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Asynchronous compression type"); -diff --git a/crypto/algboss.c b/crypto/algboss.c -index 4bde25d6..ccb85e17 100644 --- a/crypto/algboss.c +++ b/crypto/algboss.c -@@ -247,17 +247,9 @@ static int cryptomgr_schedule_test(struct crypto_alg *alg) +@@ -247,17 +247,9 @@ static int cryptomgr_schedule_test(struc memcpy(param->alg, alg->cra_name, sizeof(param->alg)); type = alg->cra_flags; @@ -380,11 +375,9 @@ index 4bde25d6..ccb85e17 100644 param->type = type; -diff --git a/crypto/crypto_user.c b/crypto/crypto_user.c -index 1c570548..a90404a0 100644 --- a/crypto/crypto_user.c +++ b/crypto/crypto_user.c -@@ -112,6 +112,21 @@ static int crypto_report_comp(struct sk_buff *skb, struct crypto_alg *alg) +@@ -112,6 +112,21 @@ nla_put_failure: return -EMSGSIZE; } @@ -406,7 +399,7 @@ index 1c570548..a90404a0 100644 static int crypto_report_akcipher(struct sk_buff *skb, struct crypto_alg *alg) { struct crypto_report_akcipher rakcipher; -@@ -186,7 +201,11 @@ static int crypto_report_one(struct crypto_alg *alg, +@@ -186,7 +201,11 @@ static int crypto_report_one(struct cryp goto nla_put_failure; break; @@ -418,9 +411,6 @@ index 1c570548..a90404a0 100644 case CRYPTO_ALG_TYPE_AKCIPHER: if (crypto_report_akcipher(skb, alg)) goto nla_put_failure; -diff --git a/crypto/scompress.c b/crypto/scompress.c -new file mode 100644 -index 00000000..35e396d1 --- /dev/null +++ b/crypto/scompress.c @@ -0,0 +1,356 @@ @@ -780,8 +770,6 @@ index 00000000..35e396d1 + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Synchronous compression type"); -diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c -index ae22f05d..bbb35eed 100644 --- a/crypto/tcrypt.c +++ b/crypto/tcrypt.c @@ -74,7 +74,7 @@ static char *check[] = { @@ -793,7 +781,7 @@ index ae22f05d..bbb35eed 100644 }; struct tcrypt_result { -@@ -1329,6 +1329,10 @@ static int do_test(const char *alg, u32 type, u32 mask, int m) +@@ -1333,6 +1333,10 @@ static int do_test(const char *alg, u32 ret += tcrypt_test("hmac(sha3-512)"); break; @@ -804,7 +792,7 @@ index ae22f05d..bbb35eed 100644 case 150: ret += tcrypt_test("ansi_cprng"); break; -@@ -1390,6 +1394,9 @@ static int do_test(const char *alg, u32 type, u32 mask, int m) +@@ -1394,6 +1398,9 @@ static int do_test(const char *alg, u32 case 190: ret += tcrypt_test("authenc(hmac(sha512),cbc(des3_ede))"); break; @@ -814,7 +802,7 @@ index ae22f05d..bbb35eed 100644 case 200: test_cipher_speed("ecb(aes)", ENCRYPT, sec, NULL, 0, speed_template_16_24_32); -@@ -1404,9 +1411,9 @@ static int do_test(const char *alg, u32 type, u32 mask, int m) +@@ -1408,9 +1415,9 @@ static int do_test(const char *alg, u32 test_cipher_speed("lrw(aes)", DECRYPT, sec, NULL, 0, speed_template_32_40_48); test_cipher_speed("xts(aes)", ENCRYPT, sec, NULL, 0, @@ -826,7 +814,7 @@ index ae22f05d..bbb35eed 100644 test_cipher_speed("cts(cbc(aes))", ENCRYPT, sec, NULL, 0, speed_template_16_24_32); test_cipher_speed("cts(cbc(aes))", DECRYPT, sec, NULL, 0, -@@ -1837,9 +1844,9 @@ static int do_test(const char *alg, u32 type, u32 mask, int m) +@@ -1841,9 +1848,9 @@ static int do_test(const char *alg, u32 test_acipher_speed("lrw(aes)", DECRYPT, sec, NULL, 0, speed_template_32_40_48); test_acipher_speed("xts(aes)", ENCRYPT, sec, NULL, 0, @@ -838,8 +826,6 @@ index ae22f05d..bbb35eed 100644 test_acipher_speed("cts(cbc(aes))", ENCRYPT, sec, NULL, 0, speed_template_16_24_32); test_acipher_speed("cts(cbc(aes))", DECRYPT, sec, NULL, 0, -diff --git a/crypto/testmgr.c b/crypto/testmgr.c -index 62dffa00..73d91fba 100644 --- a/crypto/testmgr.c +++ b/crypto/testmgr.c @@ -33,6 +33,7 @@ @@ -850,7 +836,7 @@ index 62dffa00..73d91fba 100644 #include "internal.h" -@@ -62,7 +63,7 @@ int alg_test(const char *driver, const char *alg, u32 type, u32 mask) +@@ -62,7 +63,7 @@ int alg_test(const char *driver, const c */ #define IDX1 32 #define IDX2 32400 @@ -938,7 +924,7 @@ index 62dffa00..73d91fba 100644 static void hexdump(unsigned char *buf, unsigned int len) { -@@ -202,7 +212,7 @@ static int wait_async_op(struct tcrypt_result *tr, int ret) +@@ -202,7 +212,7 @@ static int wait_async_op(struct tcrypt_r } static int ahash_partial_update(struct ahash_request **preq, @@ -947,7 +933,7 @@ index 62dffa00..73d91fba 100644 void *hash_buff, int k, int temp, struct scatterlist *sg, const char *algo, char *result, struct tcrypt_result *tresult) { -@@ -259,11 +269,12 @@ static int ahash_partial_update(struct ahash_request **preq, +@@ -259,11 +269,12 @@ out_nostate: return ret; } @@ -963,7 +949,7 @@ index 62dffa00..73d91fba 100644 unsigned int i, j, k, temp; struct scatterlist sg[8]; char *result; -@@ -274,7 +285,7 @@ static int __test_hash(struct crypto_ahash *tfm, struct hash_testvec *template, +@@ -274,7 +285,7 @@ static int __test_hash(struct crypto_aha char *xbuf[XBUFSIZE]; int ret = -ENOMEM; @@ -972,7 +958,7 @@ index 62dffa00..73d91fba 100644 if (!result) return ret; key = kmalloc(MAX_KEYLEN, GFP_KERNEL); -@@ -304,7 +315,7 @@ static int __test_hash(struct crypto_ahash *tfm, struct hash_testvec *template, +@@ -304,7 +315,7 @@ static int __test_hash(struct crypto_aha goto out; j++; @@ -981,7 +967,7 @@ index 62dffa00..73d91fba 100644 hash_buff = xbuf[0]; hash_buff += align_offset; -@@ -379,7 +390,7 @@ static int __test_hash(struct crypto_ahash *tfm, struct hash_testvec *template, +@@ -379,7 +390,7 @@ static int __test_hash(struct crypto_aha continue; j++; @@ -990,7 +976,7 @@ index 62dffa00..73d91fba 100644 temp = 0; sg_init_table(sg, template[i].np); -@@ -457,7 +468,7 @@ static int __test_hash(struct crypto_ahash *tfm, struct hash_testvec *template, +@@ -457,7 +468,7 @@ static int __test_hash(struct crypto_aha continue; j++; @@ -999,7 +985,7 @@ index 62dffa00..73d91fba 100644 ret = -EINVAL; hash_buff = xbuf[0]; -@@ -536,7 +547,8 @@ static int __test_hash(struct crypto_ahash *tfm, struct hash_testvec *template, +@@ -536,7 +547,8 @@ out_nobuf: return ret; } @@ -1009,7 +995,7 @@ index 62dffa00..73d91fba 100644 unsigned int tcount, bool use_digest) { unsigned int alignmask; -@@ -564,7 +576,7 @@ static int test_hash(struct crypto_ahash *tfm, struct hash_testvec *template, +@@ -564,7 +576,7 @@ static int test_hash(struct crypto_ahash } static int __test_aead(struct crypto_aead *tfm, int enc, @@ -1018,7 +1004,7 @@ index 62dffa00..73d91fba 100644 const bool diff_dst, const int align_offset) { const char *algo = crypto_tfm_alg_driver_name(crypto_aead_tfm(tfm)); -@@ -955,7 +967,7 @@ static int __test_aead(struct crypto_aead *tfm, int enc, +@@ -955,7 +967,7 @@ out_noxbuf: } static int test_aead(struct crypto_aead *tfm, int enc, @@ -1027,7 +1013,7 @@ index 62dffa00..73d91fba 100644 { unsigned int alignmask; int ret; -@@ -987,8 +999,236 @@ static int test_aead(struct crypto_aead *tfm, int enc, +@@ -987,8 +999,236 @@ static int test_aead(struct crypto_aead return 0; } @@ -1265,7 +1251,7 @@ index 62dffa00..73d91fba 100644 { const char *algo = crypto_tfm_alg_driver_name(crypto_cipher_tfm(tfm)); unsigned int i, j, k; -@@ -1066,7 +1306,8 @@ static int test_cipher(struct crypto_cipher *tfm, int enc, +@@ -1066,7 +1306,8 @@ out_nobuf: } static int __test_skcipher(struct crypto_skcipher *tfm, int enc, @@ -1275,7 +1261,31 @@ index 62dffa00..73d91fba 100644 const bool diff_dst, const int align_offset) { const char *algo = -@@ -1330,7 +1571,8 @@ static int __test_skcipher(struct crypto_skcipher *tfm, int enc, +@@ -1079,12 +1320,16 @@ static int __test_skcipher(struct crypto + const char *e, *d; + struct tcrypt_result result; + void *data; +- char iv[MAX_IVLEN]; ++ char *iv; + char *xbuf[XBUFSIZE]; + char *xoutbuf[XBUFSIZE]; + int ret = -ENOMEM; + unsigned int ivsize = crypto_skcipher_ivsize(tfm); + ++ iv = kmalloc(MAX_IVLEN, GFP_KERNEL); ++ if (!iv) ++ return ret; ++ + if (testmgr_alloc_buf(xbuf)) + goto out_nobuf; + +@@ -1325,12 +1570,14 @@ out: + testmgr_free_buf(xoutbuf); + out_nooutbuf: + testmgr_free_buf(xbuf); ++ kfree(iv); + out_nobuf: + return ret; } static int test_skcipher(struct crypto_skcipher *tfm, int enc, @@ -1285,7 +1295,7 @@ index 62dffa00..73d91fba 100644 { unsigned int alignmask; int ret; -@@ -1362,8 +1604,10 @@ static int test_skcipher(struct crypto_skcipher *tfm, int enc, +@@ -1362,8 +1609,10 @@ static int test_skcipher(struct crypto_s return 0; } @@ -1298,7 +1308,7 @@ index 62dffa00..73d91fba 100644 { const char *algo = crypto_tfm_alg_driver_name(crypto_comp_tfm(tfm)); unsigned int i; -@@ -1442,7 +1686,154 @@ static int test_comp(struct crypto_comp *tfm, struct comp_testvec *ctemplate, +@@ -1442,7 +1691,154 @@ out: return ret; } @@ -1454,7 +1464,7 @@ index 62dffa00..73d91fba 100644 unsigned int tcount) { const char *algo = crypto_tfm_alg_driver_name(crypto_rng_tfm(tfm)); -@@ -1509,7 +1900,7 @@ static int alg_test_aead(const struct alg_test_desc *desc, const char *driver, +@@ -1509,7 +1905,7 @@ static int alg_test_aead(const struct al struct crypto_aead *tfm; int err = 0; @@ -1463,7 +1473,7 @@ index 62dffa00..73d91fba 100644 if (IS_ERR(tfm)) { printk(KERN_ERR "alg: aead: Failed to load transform for %s: " "%ld\n", driver, PTR_ERR(tfm)); -@@ -1538,7 +1929,7 @@ static int alg_test_cipher(const struct alg_test_desc *desc, +@@ -1538,7 +1934,7 @@ static int alg_test_cipher(const struct struct crypto_cipher *tfm; int err = 0; @@ -1472,7 +1482,7 @@ index 62dffa00..73d91fba 100644 if (IS_ERR(tfm)) { printk(KERN_ERR "alg: cipher: Failed to load transform for " "%s: %ld\n", driver, PTR_ERR(tfm)); -@@ -1567,7 +1958,7 @@ static int alg_test_skcipher(const struct alg_test_desc *desc, +@@ -1567,7 +1963,7 @@ static int alg_test_skcipher(const struc struct crypto_skcipher *tfm; int err = 0; @@ -1481,7 +1491,7 @@ index 62dffa00..73d91fba 100644 if (IS_ERR(tfm)) { printk(KERN_ERR "alg: skcipher: Failed to load transform for " "%s: %ld\n", driver, PTR_ERR(tfm)); -@@ -1593,22 +1984,38 @@ static int alg_test_skcipher(const struct alg_test_desc *desc, +@@ -1593,22 +1989,38 @@ out: static int alg_test_comp(const struct alg_test_desc *desc, const char *driver, u32 type, u32 mask) { @@ -1490,7 +1500,13 @@ index 62dffa00..73d91fba 100644 + struct crypto_acomp *acomp; int err; + u32 algo_type = type & CRYPTO_ALG_TYPE_ACOMPRESS_MASK; -+ + +- tfm = crypto_alloc_comp(driver, type, mask); +- if (IS_ERR(tfm)) { +- printk(KERN_ERR "alg: comp: Failed to load transform for %s: " +- "%ld\n", driver, PTR_ERR(tfm)); +- return PTR_ERR(tfm); +- } + if (algo_type == CRYPTO_ALG_TYPE_ACOMPRESS) { + acomp = crypto_alloc_acomp(driver, type, mask); + if (IS_ERR(acomp)) { @@ -1511,13 +1527,6 @@ index 62dffa00..73d91fba 100644 + return PTR_ERR(comp); + } -- tfm = crypto_alloc_comp(driver, type, mask); -- if (IS_ERR(tfm)) { -- printk(KERN_ERR "alg: comp: Failed to load transform for %s: " -- "%ld\n", driver, PTR_ERR(tfm)); -- return PTR_ERR(tfm); -- } -- - err = test_comp(tfm, desc->suite.comp.comp.vecs, - desc->suite.comp.decomp.vecs, - desc->suite.comp.comp.count, @@ -1533,7 +1542,7 @@ index 62dffa00..73d91fba 100644 return err; } -@@ -1618,7 +2025,7 @@ static int alg_test_hash(const struct alg_test_desc *desc, const char *driver, +@@ -1618,7 +2030,7 @@ static int alg_test_hash(const struct al struct crypto_ahash *tfm; int err; @@ -1542,7 +1551,7 @@ index 62dffa00..73d91fba 100644 if (IS_ERR(tfm)) { printk(KERN_ERR "alg: hash: Failed to load transform for %s: " "%ld\n", driver, PTR_ERR(tfm)); -@@ -1646,7 +2053,7 @@ static int alg_test_crc32c(const struct alg_test_desc *desc, +@@ -1646,7 +2058,7 @@ static int alg_test_crc32c(const struct if (err) goto out; @@ -1551,7 +1560,7 @@ index 62dffa00..73d91fba 100644 if (IS_ERR(tfm)) { printk(KERN_ERR "alg: crc32c: Failed to load transform for %s: " "%ld\n", driver, PTR_ERR(tfm)); -@@ -1688,7 +2095,7 @@ static int alg_test_cprng(const struct alg_test_desc *desc, const char *driver, +@@ -1688,7 +2100,7 @@ static int alg_test_cprng(const struct a struct crypto_rng *rng; int err; @@ -1560,7 +1569,7 @@ index 62dffa00..73d91fba 100644 if (IS_ERR(rng)) { printk(KERN_ERR "alg: cprng: Failed to load transform for %s: " "%ld\n", driver, PTR_ERR(rng)); -@@ -1703,7 +2110,7 @@ static int alg_test_cprng(const struct alg_test_desc *desc, const char *driver, +@@ -1703,7 +2115,7 @@ static int alg_test_cprng(const struct a } @@ -1569,7 +1578,7 @@ index 62dffa00..73d91fba 100644 const char *driver, u32 type, u32 mask) { int ret = -EAGAIN; -@@ -1715,7 +2122,7 @@ static int drbg_cavs_test(struct drbg_testvec *test, int pr, +@@ -1715,7 +2127,7 @@ static int drbg_cavs_test(struct drbg_te if (!buf) return -ENOMEM; @@ -1578,7 +1587,7 @@ index 62dffa00..73d91fba 100644 if (IS_ERR(drng)) { printk(KERN_ERR "alg: drbg: could not allocate DRNG handle for " "%s\n", driver); -@@ -1777,7 +2184,7 @@ static int alg_test_drbg(const struct alg_test_desc *desc, const char *driver, +@@ -1777,7 +2189,7 @@ static int alg_test_drbg(const struct al int err = 0; int pr = 0; int i = 0; @@ -1587,7 +1596,7 @@ index 62dffa00..73d91fba 100644 unsigned int tcount = desc->suite.drbg.count; if (0 == memcmp(driver, "drbg_pr_", 8)) -@@ -1796,7 +2203,7 @@ static int alg_test_drbg(const struct alg_test_desc *desc, const char *driver, +@@ -1796,7 +2208,7 @@ static int alg_test_drbg(const struct al } @@ -1596,7 +1605,7 @@ index 62dffa00..73d91fba 100644 const char *alg) { struct kpp_request *req; -@@ -1888,7 +2295,7 @@ static int do_test_kpp(struct crypto_kpp *tfm, struct kpp_testvec *vec, +@@ -1888,7 +2300,7 @@ free_req: } static int test_kpp(struct crypto_kpp *tfm, const char *alg, @@ -1605,7 +1614,7 @@ index 62dffa00..73d91fba 100644 { int ret, i; -@@ -1909,7 +2316,7 @@ static int alg_test_kpp(const struct alg_test_desc *desc, const char *driver, +@@ -1909,7 +2321,7 @@ static int alg_test_kpp(const struct alg struct crypto_kpp *tfm; int err = 0; @@ -1614,7 +1623,7 @@ index 62dffa00..73d91fba 100644 if (IS_ERR(tfm)) { pr_err("alg: kpp: Failed to load tfm for %s: %ld\n", driver, PTR_ERR(tfm)); -@@ -1924,7 +2331,7 @@ static int alg_test_kpp(const struct alg_test_desc *desc, const char *driver, +@@ -1924,7 +2336,7 @@ static int alg_test_kpp(const struct alg } static int test_akcipher_one(struct crypto_akcipher *tfm, @@ -1623,7 +1632,7 @@ index 62dffa00..73d91fba 100644 { char *xbuf[XBUFSIZE]; struct akcipher_request *req; -@@ -2044,7 +2451,8 @@ static int test_akcipher_one(struct crypto_akcipher *tfm, +@@ -2044,7 +2456,8 @@ free_xbuf: } static int test_akcipher(struct crypto_akcipher *tfm, const char *alg, @@ -1633,7 +1642,7 @@ index 62dffa00..73d91fba 100644 { const char *algo = crypto_tfm_alg_driver_name(crypto_akcipher_tfm(tfm)); -@@ -2068,7 +2476,7 @@ static int alg_test_akcipher(const struct alg_test_desc *desc, +@@ -2068,7 +2481,7 @@ static int alg_test_akcipher(const struc struct crypto_akcipher *tfm; int err = 0; @@ -1642,7 +1651,7 @@ index 62dffa00..73d91fba 100644 if (IS_ERR(tfm)) { pr_err("alg: akcipher: Failed to load tfm for %s: %ld\n", driver, PTR_ERR(tfm)); -@@ -2088,112 +2496,23 @@ static int alg_test_null(const struct alg_test_desc *desc, +@@ -2088,112 +2501,23 @@ static int alg_test_null(const struct al return 0; } @@ -1760,7 +1769,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2201,12 +2520,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2201,12 +2525,7 @@ static const struct alg_test_desc alg_te .test = alg_test_aead, .suite = { .aead = { @@ -1774,7 +1783,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2214,12 +2528,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2214,12 +2533,7 @@ static const struct alg_test_desc alg_te .test = alg_test_aead, .suite = { .aead = { @@ -1788,7 +1797,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2228,12 +2537,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2228,12 +2542,7 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .aead = { @@ -1802,7 +1811,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2245,18 +2549,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2245,18 +2554,8 @@ static const struct alg_test_desc alg_te .test = alg_test_aead, .suite = { .aead = { @@ -1823,7 +1832,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2268,12 +2562,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2268,12 +2567,7 @@ static const struct alg_test_desc alg_te .test = alg_test_aead, .suite = { .aead = { @@ -1837,7 +1846,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2282,12 +2571,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2282,12 +2576,7 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .aead = { @@ -1851,7 +1860,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2296,12 +2580,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2296,12 +2585,7 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .aead = { @@ -1865,7 +1874,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2309,12 +2588,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2309,12 +2593,7 @@ static const struct alg_test_desc alg_te .test = alg_test_aead, .suite = { .aead = { @@ -1879,7 +1888,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2323,12 +2597,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2323,12 +2602,7 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .aead = { @@ -1893,7 +1902,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2344,12 +2613,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2344,12 +2618,7 @@ static const struct alg_test_desc alg_te .test = alg_test_aead, .suite = { .aead = { @@ -1907,7 +1916,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2358,12 +2622,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2358,12 +2627,7 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .aead = { @@ -1921,7 +1930,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2380,12 +2639,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2380,12 +2644,7 @@ static const struct alg_test_desc alg_te .test = alg_test_aead, .suite = { .aead = { @@ -1935,7 +1944,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2393,12 +2647,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2393,12 +2652,7 @@ static const struct alg_test_desc alg_te .test = alg_test_aead, .suite = { .aead = { @@ -1949,7 +1958,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2407,12 +2656,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2407,12 +2661,7 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .aead = { @@ -1963,7 +1972,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2429,14 +2673,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2429,14 +2678,8 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .cipher = { @@ -1980,7 +1989,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2444,14 +2682,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2444,14 +2687,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -1997,7 +2006,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2459,14 +2691,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2459,14 +2696,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2014,7 +2023,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2474,14 +2700,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2474,14 +2705,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2031,7 +2040,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2489,14 +2709,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2489,14 +2714,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2048,7 +2057,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2504,14 +2718,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2504,14 +2723,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2065,7 +2074,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2519,14 +2727,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2519,14 +2732,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2082,7 +2091,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2535,14 +2737,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2535,14 +2742,8 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .cipher = { @@ -2099,7 +2108,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2550,14 +2746,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2550,14 +2751,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2116,7 +2125,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2565,30 +2755,25 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2565,30 +2760,25 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2132,14 +2141,14 @@ index 62dffa00..73d91fba 100644 + .dec = __VECS(tf_cbc_dec_tv_template) } } -+ }, { + }, { + .alg = "cbcmac(aes)", + .fips_allowed = 1, + .test = alg_test_hash, + .suite = { + .hash = __VECS(aes_cbcmac_tv_template) + } - }, { ++ }, { .alg = "ccm(aes)", .test = alg_test_aead, .fips_allowed = 1, @@ -2158,7 +2167,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2596,14 +2781,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2596,14 +2786,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2175,7 +2184,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2611,20 +2790,14 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2611,20 +2795,14 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .test = alg_test_hash, .suite = { @@ -2198,7 +2207,7 @@ index 62dffa00..73d91fba 100644 } }, { .alg = "compress_null", -@@ -2633,94 +2806,30 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2633,94 +2811,30 @@ static const struct alg_test_desc alg_te .alg = "crc32", .test = alg_test_hash, .suite = { @@ -2230,7 +2239,7 @@ index 62dffa00..73d91fba 100644 - } + .hash = __VECS(crct10dif_tv_template) } -- }, { + }, { - .alg = "cryptd(__driver-cbc-aes-aesni)", - .test = alg_test_null, - .fips_allowed = 1, @@ -2279,7 +2288,7 @@ index 62dffa00..73d91fba 100644 - .alg = "cryptd(__ghash-pclmulqdqni)", - .test = alg_test_null, - .fips_allowed = 1, - }, { +- }, { .alg = "ctr(aes)", .test = alg_test_skcipher, .fips_allowed = 1, @@ -2298,7 +2307,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2728,14 +2837,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2728,14 +2842,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2315,7 +2324,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2743,14 +2846,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2743,14 +2851,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2332,7 +2341,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2758,14 +2855,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2758,14 +2860,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2349,7 +2358,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2773,14 +2864,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2773,14 +2869,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2366,7 +2375,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2788,29 +2873,18 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2788,29 +2878,18 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2401,7 +2410,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2818,14 +2892,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2818,14 +2897,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2418,7 +2427,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2833,14 +2901,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2833,14 +2906,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2435,7 +2444,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2848,14 +2910,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2848,14 +2915,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2452,7 +2461,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2864,14 +2920,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2864,14 +2925,8 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .comp = { @@ -2469,7 +2478,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -2879,10 +2929,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2879,10 +2934,7 @@ static const struct alg_test_desc alg_te .test = alg_test_kpp, .fips_allowed = 1, .suite = { @@ -2481,7 +2490,7 @@ index 62dffa00..73d91fba 100644 } }, { .alg = "digest_null", -@@ -2892,30 +2939,21 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2892,30 +2944,21 @@ static const struct alg_test_desc alg_te .test = alg_test_drbg, .fips_allowed = 1, .suite = { @@ -2515,7 +2524,7 @@ index 62dffa00..73d91fba 100644 } }, { /* -@@ -2930,11 +2968,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2930,11 +2973,7 @@ static const struct alg_test_desc alg_te .test = alg_test_drbg, .fips_allowed = 1, .suite = { @@ -2528,7 +2537,7 @@ index 62dffa00..73d91fba 100644 } }, { /* covered by drbg_nopr_hmac_sha256 test */ -@@ -2954,10 +2988,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2954,10 +2993,7 @@ static const struct alg_test_desc alg_te .test = alg_test_drbg, .fips_allowed = 1, .suite = { @@ -2540,7 +2549,7 @@ index 62dffa00..73d91fba 100644 } }, { /* covered by drbg_nopr_sha256 test */ -@@ -2973,10 +3004,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2973,10 +3009,7 @@ static const struct alg_test_desc alg_te .test = alg_test_drbg, .fips_allowed = 1, .suite = { @@ -2552,7 +2561,7 @@ index 62dffa00..73d91fba 100644 } }, { /* covered by drbg_pr_ctr_aes128 test */ -@@ -2996,10 +3024,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -2996,10 +3029,7 @@ static const struct alg_test_desc alg_te .test = alg_test_drbg, .fips_allowed = 1, .suite = { @@ -2564,7 +2573,7 @@ index 62dffa00..73d91fba 100644 } }, { /* covered by drbg_pr_hmac_sha256 test */ -@@ -3019,10 +3044,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3019,10 +3049,7 @@ static const struct alg_test_desc alg_te .test = alg_test_drbg, .fips_allowed = 1, .suite = { @@ -2576,15 +2585,14 @@ index 62dffa00..73d91fba 100644 } }, { /* covered by drbg_pr_sha256 test */ -@@ -3033,24 +3055,14 @@ static const struct alg_test_desc alg_test_descs[] = { - .alg = "drbg_pr_sha512", +@@ -3034,23 +3061,13 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .test = alg_test_null, -- }, { + }, { - .alg = "ecb(__aes-aesni)", - .test = alg_test_null, - .fips_allowed = 1, - }, { +- }, { .alg = "ecb(aes)", .test = alg_test_skcipher, .fips_allowed = 1, @@ -2603,7 +2611,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3058,14 +3070,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3058,14 +3075,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2620,7 +2628,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3073,14 +3079,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3073,14 +3084,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2637,7 +2645,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3088,14 +3088,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3088,14 +3093,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2654,7 +2662,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3103,14 +3097,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3103,14 +3102,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2671,7 +2679,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3118,14 +3106,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3118,14 +3111,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2688,7 +2696,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3133,14 +3115,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3133,14 +3120,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2705,7 +2713,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3151,14 +3127,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3151,14 +3132,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2722,7 +2730,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3167,14 +3137,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3167,14 +3142,8 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .cipher = { @@ -2739,7 +2747,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3197,14 +3161,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3197,14 +3166,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2756,7 +2764,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3212,14 +3170,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3212,14 +3175,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2773,7 +2781,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3227,14 +3179,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3227,14 +3184,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2790,7 +2798,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3242,14 +3188,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3242,14 +3193,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2807,7 +2815,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3257,14 +3197,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3257,14 +3202,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2824,7 +2832,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3272,14 +3206,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3272,14 +3211,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2841,7 +2849,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3287,14 +3215,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3287,14 +3220,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2858,7 +2866,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3302,14 +3224,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3302,14 +3229,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -2875,7 +2883,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3317,10 +3233,7 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3317,10 +3238,7 @@ static const struct alg_test_desc alg_te .test = alg_test_kpp, .fips_allowed = 1, .suite = { @@ -2887,7 +2895,7 @@ index 62dffa00..73d91fba 100644 } }, { .alg = "gcm(aes)", -@@ -3328,14 +3241,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3328,14 +3246,8 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .aead = { @@ -2904,7 +2912,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3343,136 +3250,94 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3343,136 +3255,94 @@ static const struct alg_test_desc alg_te .test = alg_test_hash, .fips_allowed = 1, .suite = { @@ -3055,7 +3063,7 @@ index 62dffa00..73d91fba 100644 } }, { .alg = "jitterentropy_rng", -@@ -3484,14 +3349,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3484,14 +3354,8 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .cipher = { @@ -3072,7 +3080,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3499,14 +3358,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3499,14 +3363,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -3089,7 +3097,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3514,14 +3367,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3514,14 +3372,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -3106,7 +3114,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3529,14 +3376,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3529,14 +3381,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -3123,7 +3131,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3544,14 +3385,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3544,14 +3390,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -3140,7 +3148,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3559,14 +3394,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3559,14 +3399,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -3157,7 +3165,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3575,14 +3404,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3575,14 +3409,8 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .comp = { @@ -3174,7 +3182,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3591,14 +3414,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3591,14 +3419,8 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .comp = { @@ -3191,7 +3199,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3607,42 +3424,27 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3607,42 +3429,27 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .comp = { @@ -3239,7 +3247,7 @@ index 62dffa00..73d91fba 100644 } }, { .alg = "ofb(aes)", -@@ -3650,14 +3452,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3650,14 +3457,8 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .cipher = { @@ -3256,7 +3264,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3665,24 +3461,15 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3665,24 +3466,15 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -3284,7 +3292,7 @@ index 62dffa00..73d91fba 100644 } }, { .alg = "rfc3686(ctr(aes))", -@@ -3690,14 +3477,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3690,14 +3482,8 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .cipher = { @@ -3301,7 +3309,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3706,14 +3487,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3706,14 +3492,8 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .aead = { @@ -3318,7 +3326,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3722,14 +3497,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3722,14 +3502,8 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .aead = { @@ -3335,7 +3343,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3737,14 +3506,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3737,14 +3511,8 @@ static const struct alg_test_desc alg_te .test = alg_test_aead, .suite = { .aead = { @@ -3352,7 +3360,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3752,14 +3515,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3752,14 +3520,8 @@ static const struct alg_test_desc alg_te .test = alg_test_aead, .suite = { .aead = { @@ -3369,7 +3377,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3767,71 +3524,47 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3767,71 +3529,47 @@ static const struct alg_test_desc alg_te .test = alg_test_aead, .suite = { .aead = { @@ -3449,7 +3457,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -3839,162 +3572,120 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -3839,162 +3577,120 @@ static const struct alg_test_desc alg_te .test = alg_test_hash, .fips_allowed = 1, .suite = { @@ -3637,7 +3645,7 @@ index 62dffa00..73d91fba 100644 } }, { .alg = "xts(aes)", -@@ -4002,14 +3693,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -4002,14 +3698,8 @@ static const struct alg_test_desc alg_te .fips_allowed = 1, .suite = { .cipher = { @@ -3654,7 +3662,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -4017,14 +3702,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -4017,14 +3707,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -3671,7 +3679,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -4032,14 +3711,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -4032,14 +3716,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -3688,7 +3696,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -4047,14 +3720,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -4047,14 +3725,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -3705,7 +3713,7 @@ index 62dffa00..73d91fba 100644 } } }, { -@@ -4062,14 +3729,8 @@ static const struct alg_test_desc alg_test_descs[] = { +@@ -4062,14 +3734,8 @@ static const struct alg_test_desc alg_te .test = alg_test_skcipher, .suite = { .cipher = { @@ -3722,8 +3730,6 @@ index 62dffa00..73d91fba 100644 } } } -diff --git a/crypto/testmgr.h b/crypto/testmgr.h -index 9033088c..ce9f4334 100644 --- a/crypto/testmgr.h +++ b/crypto/testmgr.h @@ -34,9 +34,9 @@ @@ -3893,12 +3899,10 @@ index 9033088c..ce9f4334 100644 +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ - #else --#define RSA_TEST_VECTORS 5 ++#else + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ - #endif --static struct akcipher_testvec rsa_tv_template[] = { ++#endif + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, @@ -3996,10 +4000,12 @@ index 9033088c..ce9f4334 100644 +#ifdef __LITTLE_ENDIAN + .key = "\x08\x00" /* rta length */ + "\x01\x00" /* rta type */ -+#else + #else +-#define RSA_TEST_VECTORS 5 + .key = "\x00\x08" /* rta length */ + "\x00\x01" /* rta type */ -+#endif + #endif +-static struct akcipher_testvec rsa_tv_template[] = { + "\x00\x00\x00\x10" /* enc key length */ + "authenticationkey20benckeyis16_bytes", + .klen = 8 + 20 + 16, @@ -4075,7 +4081,7 @@ index 9033088c..ce9f4334 100644 { #ifndef CONFIG_CRYPTO_FIPS .key = -@@ -340,6 +554,7 @@ static struct akcipher_testvec rsa_tv_template[] = { +@@ -340,6 +554,7 @@ static struct akcipher_testvec rsa_tv_te .m_size = 8, .c_size = 256, .public_key_vec = true, @@ -4083,7 +4089,7 @@ index 9033088c..ce9f4334 100644 }, { .key = "\x30\x82\x09\x29" /* sequence of 2345 bytes */ -@@ -538,12 +753,11 @@ static struct akcipher_testvec rsa_tv_template[] = { +@@ -538,12 +753,11 @@ static struct akcipher_testvec rsa_tv_te .key_len = 2349, .m_size = 8, .c_size = 512, @@ -4112,7 +4118,7 @@ index 9033088c..ce9f4334 100644 { #ifndef CONFIG_CRYPTO_FIPS .secret = -@@ -856,9 +1065,7 @@ struct kpp_testvec ecdh_tv_template[] = { +@@ -856,9 +1065,7 @@ struct kpp_testvec ecdh_tv_template[] = /* * MD4 test vectors from RFC1320 */ @@ -4123,7 +4129,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .digest = "\x31\xd6\xcf\xe0\xd1\x6a\xe9\x31" -@@ -899,8 +1106,7 @@ static struct hash_testvec md4_tv_template [] = { +@@ -899,8 +1106,7 @@ static struct hash_testvec md4_tv_templa }, }; @@ -4133,7 +4139,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .digest = "\x6b\x4e\x03\x42\x36\x67\xdb\xb7" -@@ -925,8 +1131,7 @@ static struct hash_testvec sha3_224_tv_template[] = { +@@ -925,8 +1131,7 @@ static struct hash_testvec sha3_224_tv_t }, }; @@ -4143,7 +4149,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .digest = "\xa7\xff\xc6\xf8\xbf\x1e\xd7\x66" -@@ -952,8 +1157,7 @@ static struct hash_testvec sha3_256_tv_template[] = { +@@ -952,8 +1157,7 @@ static struct hash_testvec sha3_256_tv_t }; @@ -4153,7 +4159,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .digest = "\x0c\x63\xa7\x5b\x84\x5e\x4f\x7d" -@@ -985,8 +1189,7 @@ static struct hash_testvec sha3_384_tv_template[] = { +@@ -985,8 +1189,7 @@ static struct hash_testvec sha3_384_tv_t }; @@ -4163,7 +4169,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .digest = "\xa6\x9f\x73\xcc\xa2\x3a\x9a\xc5" -@@ -1027,9 +1230,7 @@ static struct hash_testvec sha3_512_tv_template[] = { +@@ -1027,9 +1230,7 @@ static struct hash_testvec sha3_512_tv_t /* * MD5 test vectors from RFC1321 */ @@ -4174,7 +4180,7 @@ index 9033088c..ce9f4334 100644 { .digest = "\xd4\x1d\x8c\xd9\x8f\x00\xb2\x04" "\xe9\x80\x09\x98\xec\xf8\x42\x7e", -@@ -1073,9 +1274,7 @@ static struct hash_testvec md5_tv_template[] = { +@@ -1073,9 +1274,7 @@ static struct hash_testvec md5_tv_templa /* * RIPEMD-128 test vectors from ISO/IEC 10118-3:2004(E) */ @@ -4185,7 +4191,7 @@ index 9033088c..ce9f4334 100644 { .digest = "\xcd\xf2\x62\x13\xa1\x50\xdc\x3e" "\xcb\x61\x0f\x18\xf6\xb3\x8b\x46", -@@ -1137,9 +1336,7 @@ static struct hash_testvec rmd128_tv_template[] = { +@@ -1137,9 +1336,7 @@ static struct hash_testvec rmd128_tv_tem /* * RIPEMD-160 test vectors from ISO/IEC 10118-3:2004(E) */ @@ -4196,7 +4202,7 @@ index 9033088c..ce9f4334 100644 { .digest = "\x9c\x11\x85\xa5\xc5\xe9\xfc\x54\x61\x28" "\x08\x97\x7e\xe8\xf5\x48\xb2\x25\x8d\x31", -@@ -1201,9 +1398,7 @@ static struct hash_testvec rmd160_tv_template[] = { +@@ -1201,9 +1398,7 @@ static struct hash_testvec rmd160_tv_tem /* * RIPEMD-256 test vectors */ @@ -4207,7 +4213,7 @@ index 9033088c..ce9f4334 100644 { .digest = "\x02\xba\x4c\x4e\x5f\x8e\xcd\x18" "\x77\xfc\x52\xd6\x4d\x30\xe3\x7a" -@@ -1269,9 +1464,7 @@ static struct hash_testvec rmd256_tv_template[] = { +@@ -1269,9 +1464,7 @@ static struct hash_testvec rmd256_tv_tem /* * RIPEMD-320 test vectors */ @@ -4218,7 +4224,7 @@ index 9033088c..ce9f4334 100644 { .digest = "\x22\xd6\x5d\x56\x61\x53\x6c\xdc\x75\xc1" "\xfd\xf5\xc6\xde\x7b\x41\xb9\xf2\x73\x25" -@@ -1334,36 +1527,49 @@ static struct hash_testvec rmd320_tv_template[] = { +@@ -1334,36 +1527,49 @@ static struct hash_testvec rmd320_tv_tem } }; @@ -4297,7 +4303,7 @@ index 9033088c..ce9f4334 100644 } }; -@@ -1371,9 +1577,7 @@ static struct hash_testvec crct10dif_tv_template[] = { +@@ -1371,9 +1577,7 @@ static struct hash_testvec crct10dif_tv_ * SHA1 test vectors from from FIPS PUB 180-1 * Long vector from CAVS 5.0 */ @@ -4308,7 +4314,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .psize = 0, -@@ -1563,9 +1767,7 @@ static struct hash_testvec sha1_tv_template[] = { +@@ -1563,9 +1767,7 @@ static struct hash_testvec sha1_tv_templ /* * SHA224 test vectors from from FIPS PUB 180-2 */ @@ -4319,7 +4325,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .psize = 0, -@@ -1737,9 +1939,7 @@ static struct hash_testvec sha224_tv_template[] = { +@@ -1737,9 +1939,7 @@ static struct hash_testvec sha224_tv_tem /* * SHA256 test vectors from from NIST */ @@ -4330,7 +4336,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .psize = 0, -@@ -1910,9 +2110,7 @@ static struct hash_testvec sha256_tv_template[] = { +@@ -1910,9 +2110,7 @@ static struct hash_testvec sha256_tv_tem /* * SHA384 test vectors from from NIST and kerneli */ @@ -4341,7 +4347,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .psize = 0, -@@ -2104,9 +2302,7 @@ static struct hash_testvec sha384_tv_template[] = { +@@ -2104,9 +2302,7 @@ static struct hash_testvec sha384_tv_tem /* * SHA512 test vectors from from NIST and kerneli */ @@ -4352,7 +4358,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .psize = 0, -@@ -2313,9 +2509,7 @@ static struct hash_testvec sha512_tv_template[] = { +@@ -2313,9 +2509,7 @@ static struct hash_testvec sha512_tv_tem * by Vincent Rijmen and Paulo S. L. M. Barreto as part of the NESSIE * submission */ @@ -4363,7 +4369,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .psize = 0, -@@ -2411,9 +2605,7 @@ static struct hash_testvec wp512_tv_template[] = { +@@ -2411,9 +2605,7 @@ static struct hash_testvec wp512_tv_temp }, }; @@ -4374,7 +4380,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .psize = 0, -@@ -2493,9 +2685,7 @@ static struct hash_testvec wp384_tv_template[] = { +@@ -2493,9 +2685,7 @@ static struct hash_testvec wp384_tv_temp }, }; @@ -4385,7 +4391,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .psize = 0, -@@ -2562,9 +2752,7 @@ static struct hash_testvec wp256_tv_template[] = { +@@ -2562,9 +2752,7 @@ static struct hash_testvec wp256_tv_temp /* * TIGER test vectors from Tiger website */ @@ -4396,7 +4402,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .psize = 0, -@@ -2607,9 +2795,7 @@ static struct hash_testvec tgr192_tv_template[] = { +@@ -2607,9 +2795,7 @@ static struct hash_testvec tgr192_tv_tem }, }; @@ -4407,7 +4413,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .psize = 0, -@@ -2652,9 +2838,7 @@ static struct hash_testvec tgr160_tv_template[] = { +@@ -2652,9 +2838,7 @@ static struct hash_testvec tgr160_tv_tem }, }; @@ -4418,7 +4424,7 @@ index 9033088c..ce9f4334 100644 { .plaintext = "", .psize = 0, -@@ -2691,9 +2875,7 @@ static struct hash_testvec tgr128_tv_template[] = { +@@ -2691,9 +2875,7 @@ static struct hash_testvec tgr128_tv_tem }, }; @@ -4429,7 +4435,7 @@ index 9033088c..ce9f4334 100644 { { .key = "\xdf\xa6\xbf\x4d\xed\x81\xdb\x03" -@@ -2808,9 +2990,7 @@ static struct hash_testvec ghash_tv_template[] = +@@ -2808,9 +2990,7 @@ static struct hash_testvec ghash_tv_temp * HMAC-MD5 test vectors from RFC2202 * (These need to be fixed to not use strlen). */ @@ -4440,7 +4446,7 @@ index 9033088c..ce9f4334 100644 { { .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b", -@@ -2890,9 +3070,7 @@ static struct hash_testvec hmac_md5_tv_template[] = +@@ -2890,9 +3070,7 @@ static struct hash_testvec hmac_md5_tv_t /* * HMAC-RIPEMD128 test vectors from RFC2286 */ @@ -4451,7 +4457,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b", .ksize = 16, -@@ -2971,9 +3149,7 @@ static struct hash_testvec hmac_rmd128_tv_template[] = { +@@ -2971,9 +3149,7 @@ static struct hash_testvec hmac_rmd128_t /* * HMAC-RIPEMD160 test vectors from RFC2286 */ @@ -4462,7 +4468,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b", .ksize = 20, -@@ -3052,9 +3228,7 @@ static struct hash_testvec hmac_rmd160_tv_template[] = { +@@ -3052,9 +3228,7 @@ static struct hash_testvec hmac_rmd160_t /* * HMAC-SHA1 test vectors from RFC2202 */ @@ -4473,7 +4479,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b", .ksize = 20, -@@ -3135,9 +3309,7 @@ static struct hash_testvec hmac_sha1_tv_template[] = { +@@ -3135,9 +3309,7 @@ static struct hash_testvec hmac_sha1_tv_ /* * SHA224 HMAC test vectors from RFC4231 */ @@ -4484,7 +4490,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" -@@ -3250,9 +3422,7 @@ static struct hash_testvec hmac_sha224_tv_template[] = { +@@ -3250,9 +3422,7 @@ static struct hash_testvec hmac_sha224_t * HMAC-SHA256 test vectors from * draft-ietf-ipsec-ciph-sha-256-01.txt */ @@ -4495,7 +4501,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x01\x02\x03\x04\x05\x06\x07\x08" "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10" -@@ -3387,9 +3557,7 @@ static struct hash_testvec hmac_sha256_tv_template[] = { +@@ -3387,9 +3557,7 @@ static struct hash_testvec hmac_sha256_t }, }; @@ -4506,7 +4512,7 @@ index 9033088c..ce9f4334 100644 { /* From NIST Special Publication 800-38B, AES-128 */ .key = "\x2b\x7e\x15\x16\x28\xae\xd2\xa6" "\xab\xf7\x15\x88\x09\xcf\x4f\x3c", -@@ -3464,9 +3632,67 @@ static struct hash_testvec aes_cmac128_tv_template[] = { +@@ -3464,9 +3632,67 @@ static struct hash_testvec aes_cmac128_t } }; @@ -4576,7 +4582,7 @@ index 9033088c..ce9f4334 100644 /* * From NIST Special Publication 800-38B, Three Key TDEA * Corrected test vectors from: -@@ -3512,9 +3738,7 @@ static struct hash_testvec des3_ede_cmac64_tv_template[] = { +@@ -3512,9 +3738,7 @@ static struct hash_testvec des3_ede_cmac } }; @@ -4587,7 +4593,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x00\x01\x02\x03\x04\x05\x06\x07" "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f", -@@ -3580,36 +3804,35 @@ static struct hash_testvec aes_xcbc128_tv_template[] = { +@@ -3580,36 +3804,35 @@ static struct hash_testvec aes_xcbc128_t } }; @@ -4619,8 +4625,6 @@ index 9033088c..ce9f4334 100644 -static char vmac_string6[129] = {'p', 't', '*', '7', 'l', - 'i', '!', '#', 'w', '0', - 'z', '/', '4', 'A', 'n'}; -- --static struct hash_testvec aes_vmac128_tv_template[] = { +static const char vmac_string1[128] = {'\x01', '\x01', '\x01', '\x01', + '\x02', '\x03', '\x02', '\x02', + '\x02', '\x04', '\x01', '\x07', @@ -4648,12 +4652,13 @@ index 9033088c..ce9f4334 100644 +static const char vmac_string6[129] = {'p', 't', '*', '7', 'l', + 'i', '!', '#', 'w', '0', + 'z', '/', '4', 'A', 'n'}; -+ + +-static struct hash_testvec aes_vmac128_tv_template[] = { +static const struct hash_testvec aes_vmac128_tv_template[] = { { .key = "\x00\x01\x02\x03\x04\x05\x06\x07" "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f", -@@ -3687,9 +3910,7 @@ static struct hash_testvec aes_vmac128_tv_template[] = { +@@ -3687,9 +3910,7 @@ static struct hash_testvec aes_vmac128_t * SHA384 HMAC test vectors from RFC4231 */ @@ -4664,7 +4669,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" -@@ -3787,9 +4008,7 @@ static struct hash_testvec hmac_sha384_tv_template[] = { +@@ -3787,9 +4008,7 @@ static struct hash_testvec hmac_sha384_t * SHA512 HMAC test vectors from RFC4231 */ @@ -4675,7 +4680,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" -@@ -3894,9 +4113,7 @@ static struct hash_testvec hmac_sha512_tv_template[] = { +@@ -3894,9 +4113,7 @@ static struct hash_testvec hmac_sha512_t }, }; @@ -4686,7 +4691,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" -@@ -3985,9 +4202,7 @@ static struct hash_testvec hmac_sha3_224_tv_template[] = { +@@ -3985,9 +4202,7 @@ static struct hash_testvec hmac_sha3_224 }, }; @@ -4697,7 +4702,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" -@@ -4076,9 +4291,7 @@ static struct hash_testvec hmac_sha3_256_tv_template[] = { +@@ -4076,9 +4291,7 @@ static struct hash_testvec hmac_sha3_256 }, }; @@ -4708,7 +4713,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" -@@ -4175,9 +4388,7 @@ static struct hash_testvec hmac_sha3_384_tv_template[] = { +@@ -4175,9 +4388,7 @@ static struct hash_testvec hmac_sha3_384 }, }; @@ -4719,7 +4724,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" -@@ -4286,9 +4497,7 @@ static struct hash_testvec hmac_sha3_512_tv_template[] = { +@@ -4286,9 +4497,7 @@ static struct hash_testvec hmac_sha3_512 * Poly1305 test vectors from RFC7539 A.3. */ @@ -4730,7 +4735,7 @@ index 9033088c..ce9f4334 100644 { /* Test Vector #1 */ .plaintext = "\x00\x00\x00\x00\x00\x00\x00\x00" "\x00\x00\x00\x00\x00\x00\x00\x00" -@@ -4533,20 +4742,7 @@ static struct hash_testvec poly1305_tv_template[] = { +@@ -4533,20 +4742,7 @@ static struct hash_testvec poly1305_tv_t /* * DES test vectors. */ @@ -4752,7 +4757,7 @@ index 9033088c..ce9f4334 100644 { /* From Applied Cryptography */ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef", .klen = 8, -@@ -4720,7 +4916,7 @@ static struct cipher_testvec des_enc_tv_template[] = { +@@ -4720,7 +4916,7 @@ static struct cipher_testvec des_enc_tv_ }, }; @@ -4761,7 +4766,7 @@ index 9033088c..ce9f4334 100644 { /* From Applied Cryptography */ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef", .klen = 8, -@@ -4830,7 +5026,7 @@ static struct cipher_testvec des_dec_tv_template[] = { +@@ -4830,7 +5026,7 @@ static struct cipher_testvec des_dec_tv_ }, }; @@ -4770,7 +4775,7 @@ index 9033088c..ce9f4334 100644 { /* From OpenSSL */ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef", .klen = 8, -@@ -4956,7 +5152,7 @@ static struct cipher_testvec des_cbc_enc_tv_template[] = { +@@ -4956,7 +5152,7 @@ static struct cipher_testvec des_cbc_enc }, }; @@ -4779,7 +4784,7 @@ index 9033088c..ce9f4334 100644 { /* FIPS Pub 81 */ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef", .klen = 8, -@@ -5065,7 +5261,7 @@ static struct cipher_testvec des_cbc_dec_tv_template[] = { +@@ -5065,7 +5261,7 @@ static struct cipher_testvec des_cbc_dec }, }; @@ -4788,7 +4793,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\xC9\x83\xA6\xC9\xEC\x0F\x32\x55", .klen = 8, -@@ -5211,7 +5407,7 @@ static struct cipher_testvec des_ctr_enc_tv_template[] = { +@@ -5211,7 +5407,7 @@ static struct cipher_testvec des_ctr_enc }, }; @@ -4797,7 +4802,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\xC9\x83\xA6\xC9\xEC\x0F\x32\x55", .klen = 8, -@@ -5357,7 +5553,7 @@ static struct cipher_testvec des_ctr_dec_tv_template[] = { +@@ -5357,7 +5553,7 @@ static struct cipher_testvec des_ctr_dec }, }; @@ -4806,7 +4811,7 @@ index 9033088c..ce9f4334 100644 { /* These are from openssl */ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef" "\x55\x55\x55\x55\x55\x55\x55\x55" -@@ -5522,7 +5718,7 @@ static struct cipher_testvec des3_ede_enc_tv_template[] = { +@@ -5522,7 +5718,7 @@ static struct cipher_testvec des3_ede_en }, }; @@ -4815,7 +4820,7 @@ index 9033088c..ce9f4334 100644 { /* These are from openssl */ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef" "\x55\x55\x55\x55\x55\x55\x55\x55" -@@ -5687,7 +5883,7 @@ static struct cipher_testvec des3_ede_dec_tv_template[] = { +@@ -5687,7 +5883,7 @@ static struct cipher_testvec des3_ede_de }, }; @@ -4824,7 +4829,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from openssl */ .key = "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24" "\x44\x4D\x99\x5A\x12\xD6\x40\xC0" -@@ -5867,7 +6063,7 @@ static struct cipher_testvec des3_ede_cbc_enc_tv_template[] = { +@@ -5867,7 +6063,7 @@ static struct cipher_testvec des3_ede_cb }, }; @@ -4833,7 +4838,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from openssl */ .key = "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24" "\x44\x4D\x99\x5A\x12\xD6\x40\xC0" -@@ -6047,7 +6243,7 @@ static struct cipher_testvec des3_ede_cbc_dec_tv_template[] = { +@@ -6047,7 +6243,7 @@ static struct cipher_testvec des3_ede_cb }, }; @@ -4842,7 +4847,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\x9C\xD6\xF3\x9C\xB9\x5A\x67\x00" "\x5A\x67\x00\x2D\xCE\xEB\x2D\xCE" -@@ -6325,7 +6521,7 @@ static struct cipher_testvec des3_ede_ctr_enc_tv_template[] = { +@@ -6325,7 +6521,7 @@ static struct cipher_testvec des3_ede_ct }, }; @@ -4851,7 +4856,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\x9C\xD6\xF3\x9C\xB9\x5A\x67\x00" "\x5A\x67\x00\x2D\xCE\xEB\x2D\xCE" -@@ -6606,14 +6802,7 @@ static struct cipher_testvec des3_ede_ctr_dec_tv_template[] = { +@@ -6606,14 +6802,7 @@ static struct cipher_testvec des3_ede_ct /* * Blowfish test vectors. */ @@ -4867,7 +4872,7 @@ index 9033088c..ce9f4334 100644 { /* DES test vectors from OpenSSL */ .key = "\x00\x00\x00\x00\x00\x00\x00\x00", .klen = 8, -@@ -6805,7 +6994,7 @@ static struct cipher_testvec bf_enc_tv_template[] = { +@@ -6805,7 +6994,7 @@ static struct cipher_testvec bf_enc_tv_t }, }; @@ -4876,7 +4881,7 @@ index 9033088c..ce9f4334 100644 { /* DES test vectors from OpenSSL */ .key = "\x00\x00\x00\x00\x00\x00\x00\x00", .klen = 8, -@@ -6997,7 +7186,7 @@ static struct cipher_testvec bf_dec_tv_template[] = { +@@ -6997,7 +7186,7 @@ static struct cipher_testvec bf_dec_tv_t }, }; @@ -4885,7 +4890,7 @@ index 9033088c..ce9f4334 100644 { /* From OpenSSL */ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef" "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87", -@@ -7154,7 +7343,7 @@ static struct cipher_testvec bf_cbc_enc_tv_template[] = { +@@ -7154,7 +7343,7 @@ static struct cipher_testvec bf_cbc_enc_ }, }; @@ -4894,7 +4899,7 @@ index 9033088c..ce9f4334 100644 { /* From OpenSSL */ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef" "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87", -@@ -7311,7 +7500,7 @@ static struct cipher_testvec bf_cbc_dec_tv_template[] = { +@@ -7311,7 +7500,7 @@ static struct cipher_testvec bf_cbc_dec_ }, }; @@ -4903,7 +4908,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -7723,7 +7912,7 @@ static struct cipher_testvec bf_ctr_enc_tv_template[] = { +@@ -7723,7 +7912,7 @@ static struct cipher_testvec bf_ctr_enc_ }, }; @@ -4912,7 +4917,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -8138,18 +8327,7 @@ static struct cipher_testvec bf_ctr_dec_tv_template[] = { +@@ -8138,18 +8327,7 @@ static struct cipher_testvec bf_ctr_dec_ /* * Twofish test vectors. */ @@ -4932,7 +4937,7 @@ index 9033088c..ce9f4334 100644 { .key = zeroed_string, .klen = 16, -@@ -8317,7 +8495,7 @@ static struct cipher_testvec tf_enc_tv_template[] = { +@@ -8317,7 +8495,7 @@ static struct cipher_testvec tf_enc_tv_t }, }; @@ -4941,7 +4946,7 @@ index 9033088c..ce9f4334 100644 { .key = zeroed_string, .klen = 16, -@@ -8485,7 +8663,7 @@ static struct cipher_testvec tf_dec_tv_template[] = { +@@ -8485,7 +8663,7 @@ static struct cipher_testvec tf_dec_tv_t }, }; @@ -4950,7 +4955,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Nettle */ .key = zeroed_string, .klen = 16, -@@ -8668,7 +8846,7 @@ static struct cipher_testvec tf_cbc_enc_tv_template[] = { +@@ -8668,7 +8846,7 @@ static struct cipher_testvec tf_cbc_enc_ }, }; @@ -4959,7 +4964,7 @@ index 9033088c..ce9f4334 100644 { /* Reverse of the first four above */ .key = zeroed_string, .klen = 16, -@@ -8851,7 +9029,7 @@ static struct cipher_testvec tf_cbc_dec_tv_template[] = { +@@ -8851,7 +9029,7 @@ static struct cipher_testvec tf_cbc_dec_ }, }; @@ -4968,7 +4973,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -9262,7 +9440,7 @@ static struct cipher_testvec tf_ctr_enc_tv_template[] = { +@@ -9262,7 +9440,7 @@ static struct cipher_testvec tf_ctr_enc_ }, }; @@ -4977,7 +4982,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -9673,7 +9851,7 @@ static struct cipher_testvec tf_ctr_dec_tv_template[] = { +@@ -9673,7 +9851,7 @@ static struct cipher_testvec tf_ctr_dec_ }, }; @@ -4986,7 +4991,7 @@ index 9033088c..ce9f4334 100644 /* Generated from AES-LRW test vectors */ { .key = "\x45\x62\xac\x25\xf8\x28\x17\x6d" -@@ -9925,7 +10103,7 @@ static struct cipher_testvec tf_lrw_enc_tv_template[] = { +@@ -9925,7 +10103,7 @@ static struct cipher_testvec tf_lrw_enc_ }, }; @@ -4995,7 +5000,7 @@ index 9033088c..ce9f4334 100644 /* Generated from AES-LRW test vectors */ /* same as enc vectors with input and result reversed */ { -@@ -10178,7 +10356,7 @@ static struct cipher_testvec tf_lrw_dec_tv_template[] = { +@@ -10178,7 +10356,7 @@ static struct cipher_testvec tf_lrw_dec_ }, }; @@ -5004,7 +5009,7 @@ index 9033088c..ce9f4334 100644 /* Generated from AES-XTS test vectors */ { .key = "\x00\x00\x00\x00\x00\x00\x00\x00" -@@ -10520,7 +10698,7 @@ static struct cipher_testvec tf_xts_enc_tv_template[] = { +@@ -10520,7 +10698,7 @@ static struct cipher_testvec tf_xts_enc_ }, }; @@ -5013,7 +5018,7 @@ index 9033088c..ce9f4334 100644 /* Generated from AES-XTS test vectors */ /* same as enc vectors with input and result reversed */ { -@@ -10867,25 +11045,7 @@ static struct cipher_testvec tf_xts_dec_tv_template[] = { +@@ -10867,25 +11045,7 @@ static struct cipher_testvec tf_xts_dec_ * Serpent test vectors. These are backwards because Serpent writes * octet sequences in right-to-left mode. */ @@ -5040,7 +5045,7 @@ index 9033088c..ce9f4334 100644 { .input = "\x00\x01\x02\x03\x04\x05\x06\x07" "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f", -@@ -11061,7 +11221,7 @@ static struct cipher_testvec serpent_enc_tv_template[] = { +@@ -11061,7 +11221,7 @@ static struct cipher_testvec serpent_enc }, }; @@ -5049,7 +5054,7 @@ index 9033088c..ce9f4334 100644 { /* KeySize=128, PT=0, I=1 */ .input = "\x00\x00\x00\x00\x00\x00\x00\x00" "\x00\x00\x00\x00\x00\x00\x00\x00", -@@ -11111,7 +11271,7 @@ static struct cipher_testvec tnepres_enc_tv_template[] = { +@@ -11111,7 +11271,7 @@ static struct cipher_testvec tnepres_enc }; @@ -5058,7 +5063,7 @@ index 9033088c..ce9f4334 100644 { .input = "\x12\x07\xfc\xce\x9b\xd0\xd6\x47" "\x6a\xe9\x8f\xbe\xd1\x43\xa0\xe2", -@@ -11287,7 +11447,7 @@ static struct cipher_testvec serpent_dec_tv_template[] = { +@@ -11287,7 +11447,7 @@ static struct cipher_testvec serpent_dec }, }; @@ -5067,7 +5072,7 @@ index 9033088c..ce9f4334 100644 { .input = "\x41\xcc\x6b\x31\x59\x31\x45\x97" "\x6d\x6f\xbb\x38\x4b\x37\x21\x28", -@@ -11328,7 +11488,7 @@ static struct cipher_testvec tnepres_dec_tv_template[] = { +@@ -11328,7 +11488,7 @@ static struct cipher_testvec tnepres_dec }, }; @@ -5076,7 +5081,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -11469,7 +11629,7 @@ static struct cipher_testvec serpent_cbc_enc_tv_template[] = { +@@ -11469,7 +11629,7 @@ static struct cipher_testvec serpent_cbc }, }; @@ -5085,7 +5090,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -11610,7 +11770,7 @@ static struct cipher_testvec serpent_cbc_dec_tv_template[] = { +@@ -11610,7 +11770,7 @@ static struct cipher_testvec serpent_cbc }, }; @@ -5094,7 +5099,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -12021,7 +12181,7 @@ static struct cipher_testvec serpent_ctr_enc_tv_template[] = { +@@ -12021,7 +12181,7 @@ static struct cipher_testvec serpent_ctr }, }; @@ -5103,7 +5108,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -12432,7 +12592,7 @@ static struct cipher_testvec serpent_ctr_dec_tv_template[] = { +@@ -12432,7 +12592,7 @@ static struct cipher_testvec serpent_ctr }, }; @@ -5112,7 +5117,7 @@ index 9033088c..ce9f4334 100644 /* Generated from AES-LRW test vectors */ { .key = "\x45\x62\xac\x25\xf8\x28\x17\x6d" -@@ -12684,7 +12844,7 @@ static struct cipher_testvec serpent_lrw_enc_tv_template[] = { +@@ -12684,7 +12844,7 @@ static struct cipher_testvec serpent_lrw }, }; @@ -5121,7 +5126,7 @@ index 9033088c..ce9f4334 100644 /* Generated from AES-LRW test vectors */ /* same as enc vectors with input and result reversed */ { -@@ -12937,7 +13097,7 @@ static struct cipher_testvec serpent_lrw_dec_tv_template[] = { +@@ -12937,7 +13097,7 @@ static struct cipher_testvec serpent_lrw }, }; @@ -5130,7 +5135,7 @@ index 9033088c..ce9f4334 100644 /* Generated from AES-XTS test vectors */ { .key = "\x00\x00\x00\x00\x00\x00\x00\x00" -@@ -13279,7 +13439,7 @@ static struct cipher_testvec serpent_xts_enc_tv_template[] = { +@@ -13279,7 +13439,7 @@ static struct cipher_testvec serpent_xts }, }; @@ -5139,7 +5144,7 @@ index 9033088c..ce9f4334 100644 /* Generated from AES-XTS test vectors */ /* same as enc vectors with input and result reversed */ { -@@ -13623,18 +13783,7 @@ static struct cipher_testvec serpent_xts_dec_tv_template[] = { +@@ -13623,18 +13783,7 @@ static struct cipher_testvec serpent_xts }; /* Cast6 test vectors from RFC 2612 */ @@ -5159,7 +5164,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x23\x42\xbb\x9e\xfa\x38\x54\x2c" "\x0a\xf7\x56\x47\xf2\x9f\x61\x5d", -@@ -13805,7 +13954,7 @@ static struct cipher_testvec cast6_enc_tv_template[] = { +@@ -13805,7 +13954,7 @@ static struct cipher_testvec cast6_enc_t }, }; @@ -5168,7 +5173,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x23\x42\xbb\x9e\xfa\x38\x54\x2c" "\x0a\xf7\x56\x47\xf2\x9f\x61\x5d", -@@ -13976,7 +14125,7 @@ static struct cipher_testvec cast6_dec_tv_template[] = { +@@ -13976,7 +14125,7 @@ static struct cipher_testvec cast6_dec_t }, }; @@ -5177,7 +5182,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from TF test vectors */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -14117,7 +14266,7 @@ static struct cipher_testvec cast6_cbc_enc_tv_template[] = { +@@ -14117,7 +14266,7 @@ static struct cipher_testvec cast6_cbc_e }, }; @@ -5186,7 +5191,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from TF test vectors */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -14258,7 +14407,7 @@ static struct cipher_testvec cast6_cbc_dec_tv_template[] = { +@@ -14258,7 +14407,7 @@ static struct cipher_testvec cast6_cbc_d }, }; @@ -5195,7 +5200,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from TF test vectors */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -14415,7 +14564,7 @@ static struct cipher_testvec cast6_ctr_enc_tv_template[] = { +@@ -14415,7 +14564,7 @@ static struct cipher_testvec cast6_ctr_e }, }; @@ -5204,7 +5209,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from TF test vectors */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -14572,7 +14721,7 @@ static struct cipher_testvec cast6_ctr_dec_tv_template[] = { +@@ -14572,7 +14721,7 @@ static struct cipher_testvec cast6_ctr_d }, }; @@ -5213,7 +5218,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from TF test vectors */ .key = "\xf8\xd4\x76\xff\xd6\x46\xee\x6c" "\x23\x84\xcb\x1c\x77\xd6\x19\x5d" -@@ -14719,7 +14868,7 @@ static struct cipher_testvec cast6_lrw_enc_tv_template[] = { +@@ -14719,7 +14868,7 @@ static struct cipher_testvec cast6_lrw_e }, }; @@ -5222,7 +5227,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from TF test vectors */ .key = "\xf8\xd4\x76\xff\xd6\x46\xee\x6c" "\x23\x84\xcb\x1c\x77\xd6\x19\x5d" -@@ -14866,7 +15015,7 @@ static struct cipher_testvec cast6_lrw_dec_tv_template[] = { +@@ -14866,7 +15015,7 @@ static struct cipher_testvec cast6_lrw_d }, }; @@ -5231,7 +5236,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from TF test vectors */ .key = "\x27\x18\x28\x18\x28\x45\x90\x45" "\x23\x53\x60\x28\x74\x71\x35\x26" -@@ -15015,7 +15164,7 @@ static struct cipher_testvec cast6_xts_enc_tv_template[] = { +@@ -15015,7 +15164,7 @@ static struct cipher_testvec cast6_xts_e }, }; @@ -5240,7 +5245,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from TF test vectors */ .key = "\x27\x18\x28\x18\x28\x45\x90\x45" "\x23\x53\x60\x28\x74\x71\x35\x26" -@@ -15168,39 +15317,7 @@ static struct cipher_testvec cast6_xts_dec_tv_template[] = { +@@ -15168,39 +15317,7 @@ static struct cipher_testvec cast6_xts_d /* * AES test vectors. */ @@ -5281,7 +5286,7 @@ index 9033088c..ce9f4334 100644 { /* From FIPS-197 */ .key = "\x00\x01\x02\x03\x04\x05\x06\x07" "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f", -@@ -15372,7 +15489,7 @@ static struct cipher_testvec aes_enc_tv_template[] = { +@@ -15372,7 +15489,7 @@ static struct cipher_testvec aes_enc_tv_ }, }; @@ -5290,7 +5295,7 @@ index 9033088c..ce9f4334 100644 { /* From FIPS-197 */ .key = "\x00\x01\x02\x03\x04\x05\x06\x07" "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f", -@@ -15544,7 +15661,7 @@ static struct cipher_testvec aes_dec_tv_template[] = { +@@ -15544,7 +15661,7 @@ static struct cipher_testvec aes_dec_tv_ }, }; @@ -5299,7 +5304,7 @@ index 9033088c..ce9f4334 100644 { /* From RFC 3602 */ .key = "\x06\xa9\x21\x40\x36\xb8\xa1\x5b" "\x51\x2e\x03\xd5\x34\x12\x00\x06", -@@ -15766,7 +15883,7 @@ static struct cipher_testvec aes_cbc_enc_tv_template[] = { +@@ -15766,7 +15883,7 @@ static struct cipher_testvec aes_cbc_enc }, }; @@ -5308,7 +5313,7 @@ index 9033088c..ce9f4334 100644 { /* From RFC 3602 */ .key = "\x06\xa9\x21\x40\x36\xb8\xa1\x5b" "\x51\x2e\x03\xd5\x34\x12\x00\x06", -@@ -15988,7 +16105,7 @@ static struct cipher_testvec aes_cbc_dec_tv_template[] = { +@@ -15988,7 +16105,7 @@ static struct cipher_testvec aes_cbc_dec }, }; @@ -5317,7 +5322,7 @@ index 9033088c..ce9f4334 100644 { /* Input data from RFC 2410 Case 1 */ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -16030,7 +16147,7 @@ static struct aead_testvec hmac_md5_ecb_cipher_null_enc_tv_template[] = { +@@ -16030,7 +16147,7 @@ static struct aead_testvec hmac_md5_ecb_ }, }; @@ -5326,7 +5331,7 @@ index 9033088c..ce9f4334 100644 { #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -16072,7 +16189,7 @@ static struct aead_testvec hmac_md5_ecb_cipher_null_dec_tv_template[] = { +@@ -16072,7 +16189,7 @@ static struct aead_testvec hmac_md5_ecb_ }, }; @@ -5335,7 +5340,7 @@ index 9033088c..ce9f4334 100644 { /* RFC 3602 Case 1 */ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -16341,7 +16458,7 @@ static struct aead_testvec hmac_sha1_aes_cbc_enc_tv_temp[] = { +@@ -16341,7 +16458,7 @@ static struct aead_testvec hmac_sha1_aes }, }; @@ -5344,7 +5349,7 @@ index 9033088c..ce9f4334 100644 { /* Input data from RFC 2410 Case 1 */ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -16387,7 +16504,7 @@ static struct aead_testvec hmac_sha1_ecb_cipher_null_enc_tv_temp[] = { +@@ -16387,7 +16504,7 @@ static struct aead_testvec hmac_sha1_ecb }, }; @@ -5353,7 +5358,7 @@ index 9033088c..ce9f4334 100644 { #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -16433,7 +16550,7 @@ static struct aead_testvec hmac_sha1_ecb_cipher_null_dec_tv_temp[] = { +@@ -16433,7 +16550,7 @@ static struct aead_testvec hmac_sha1_ecb }, }; @@ -5362,7 +5367,7 @@ index 9033088c..ce9f4334 100644 { /* RFC 3602 Case 1 */ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -16716,7 +16833,7 @@ static struct aead_testvec hmac_sha256_aes_cbc_enc_tv_temp[] = { +@@ -16716,7 +16833,7 @@ static struct aead_testvec hmac_sha256_a }, }; @@ -5371,7 +5376,7 @@ index 9033088c..ce9f4334 100644 { /* RFC 3602 Case 1 */ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -17055,9 +17172,7 @@ static struct aead_testvec hmac_sha512_aes_cbc_enc_tv_temp[] = { +@@ -17055,9 +17172,7 @@ static struct aead_testvec hmac_sha512_a }, }; @@ -5382,7 +5387,7 @@ index 9033088c..ce9f4334 100644 { /*Generated with cryptopp*/ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -17116,9 +17231,7 @@ static struct aead_testvec hmac_sha1_des_cbc_enc_tv_temp[] = { +@@ -17116,9 +17231,7 @@ static struct aead_testvec hmac_sha1_des }, }; @@ -5393,7 +5398,7 @@ index 9033088c..ce9f4334 100644 { /*Generated with cryptopp*/ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -17177,9 +17290,7 @@ static struct aead_testvec hmac_sha224_des_cbc_enc_tv_temp[] = { +@@ -17177,9 +17290,7 @@ static struct aead_testvec hmac_sha224_d }, }; @@ -5404,7 +5409,7 @@ index 9033088c..ce9f4334 100644 { /*Generated with cryptopp*/ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -17240,9 +17351,7 @@ static struct aead_testvec hmac_sha256_des_cbc_enc_tv_temp[] = { +@@ -17240,9 +17351,7 @@ static struct aead_testvec hmac_sha256_d }, }; @@ -5415,7 +5420,7 @@ index 9033088c..ce9f4334 100644 { /*Generated with cryptopp*/ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -17307,9 +17416,7 @@ static struct aead_testvec hmac_sha384_des_cbc_enc_tv_temp[] = { +@@ -17307,9 +17416,7 @@ static struct aead_testvec hmac_sha384_d }, }; @@ -5426,7 +5431,7 @@ index 9033088c..ce9f4334 100644 { /*Generated with cryptopp*/ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -17378,9 +17485,7 @@ static struct aead_testvec hmac_sha512_des_cbc_enc_tv_temp[] = { +@@ -17378,9 +17485,7 @@ static struct aead_testvec hmac_sha512_d }, }; @@ -5437,7 +5442,7 @@ index 9033088c..ce9f4334 100644 { /*Generated with cryptopp*/ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -17441,9 +17546,7 @@ static struct aead_testvec hmac_sha1_des3_ede_cbc_enc_tv_temp[] = { +@@ -17441,9 +17546,7 @@ static struct aead_testvec hmac_sha1_des }, }; @@ -5448,7 +5453,7 @@ index 9033088c..ce9f4334 100644 { /*Generated with cryptopp*/ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -17504,9 +17607,7 @@ static struct aead_testvec hmac_sha224_des3_ede_cbc_enc_tv_temp[] = { +@@ -17504,9 +17607,7 @@ static struct aead_testvec hmac_sha224_d }, }; @@ -5459,7 +5464,7 @@ index 9033088c..ce9f4334 100644 { /*Generated with cryptopp*/ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -17569,9 +17670,7 @@ static struct aead_testvec hmac_sha256_des3_ede_cbc_enc_tv_temp[] = { +@@ -17569,9 +17670,7 @@ static struct aead_testvec hmac_sha256_d }, }; @@ -5470,7 +5475,7 @@ index 9033088c..ce9f4334 100644 { /*Generated with cryptopp*/ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -17638,9 +17737,7 @@ static struct aead_testvec hmac_sha384_des3_ede_cbc_enc_tv_temp[] = { +@@ -17638,9 +17737,7 @@ static struct aead_testvec hmac_sha384_d }, }; @@ -5481,7 +5486,7 @@ index 9033088c..ce9f4334 100644 { /*Generated with cryptopp*/ #ifdef __LITTLE_ENDIAN .key = "\x08\x00" /* rta length */ -@@ -17711,7 +17808,7 @@ static struct aead_testvec hmac_sha512_des3_ede_cbc_enc_tv_temp[] = { +@@ -17711,7 +17808,7 @@ static struct aead_testvec hmac_sha512_d }, }; @@ -5490,7 +5495,7 @@ index 9033088c..ce9f4334 100644 /* from http://grouper.ieee.org/groups/1619/email/pdf00017.pdf */ { /* LRW-32-AES 1 */ .key = "\x45\x62\xac\x25\xf8\x28\x17\x6d" -@@ -17964,7 +18061,7 @@ static struct cipher_testvec aes_lrw_enc_tv_template[] = { +@@ -17964,7 +18061,7 @@ static struct cipher_testvec aes_lrw_enc } }; @@ -5499,7 +5504,7 @@ index 9033088c..ce9f4334 100644 /* from http://grouper.ieee.org/groups/1619/email/pdf00017.pdf */ /* same as enc vectors with input and result reversed */ { /* LRW-32-AES 1 */ -@@ -18218,7 +18315,7 @@ static struct cipher_testvec aes_lrw_dec_tv_template[] = { +@@ -18218,7 +18315,7 @@ static struct cipher_testvec aes_lrw_dec } }; @@ -5508,7 +5513,7 @@ index 9033088c..ce9f4334 100644 /* http://grouper.ieee.org/groups/1619/email/pdf00086.pdf */ { /* XTS-AES 1 */ .key = "\x00\x00\x00\x00\x00\x00\x00\x00" -@@ -18561,7 +18658,7 @@ static struct cipher_testvec aes_xts_enc_tv_template[] = { +@@ -18561,7 +18658,7 @@ static struct cipher_testvec aes_xts_enc } }; @@ -5517,7 +5522,7 @@ index 9033088c..ce9f4334 100644 /* http://grouper.ieee.org/groups/1619/email/pdf00086.pdf */ { /* XTS-AES 1 */ .key = "\x00\x00\x00\x00\x00\x00\x00\x00" -@@ -18905,7 +19002,7 @@ static struct cipher_testvec aes_xts_dec_tv_template[] = { +@@ -18905,7 +19002,7 @@ static struct cipher_testvec aes_xts_dec }; @@ -5526,7 +5531,7 @@ index 9033088c..ce9f4334 100644 { /* From NIST Special Publication 800-38A, Appendix F.5 */ .key = "\x2b\x7e\x15\x16\x28\xae\xd2\xa6" "\xab\xf7\x15\x88\x09\xcf\x4f\x3c", -@@ -19260,7 +19357,7 @@ static struct cipher_testvec aes_ctr_enc_tv_template[] = { +@@ -19260,7 +19357,7 @@ static struct cipher_testvec aes_ctr_enc }, }; @@ -5535,7 +5540,7 @@ index 9033088c..ce9f4334 100644 { /* From NIST Special Publication 800-38A, Appendix F.5 */ .key = "\x2b\x7e\x15\x16\x28\xae\xd2\xa6" "\xab\xf7\x15\x88\x09\xcf\x4f\x3c", -@@ -19615,7 +19712,7 @@ static struct cipher_testvec aes_ctr_dec_tv_template[] = { +@@ -19615,7 +19712,7 @@ static struct cipher_testvec aes_ctr_dec }, }; @@ -5544,7 +5549,7 @@ index 9033088c..ce9f4334 100644 { /* From RFC 3686 */ .key = "\xae\x68\x52\xf8\x12\x10\x67\xcc" "\x4b\xf7\xa5\x76\x55\x77\xf3\x9e" -@@ -20747,7 +20844,7 @@ static struct cipher_testvec aes_ctr_rfc3686_enc_tv_template[] = { +@@ -20747,7 +20844,7 @@ static struct cipher_testvec aes_ctr_rfc }, }; @@ -5553,7 +5558,7 @@ index 9033088c..ce9f4334 100644 { /* From RFC 3686 */ .key = "\xae\x68\x52\xf8\x12\x10\x67\xcc" "\x4b\xf7\xa5\x76\x55\x77\xf3\x9e" -@@ -20838,7 +20935,7 @@ static struct cipher_testvec aes_ctr_rfc3686_dec_tv_template[] = { +@@ -20838,7 +20935,7 @@ static struct cipher_testvec aes_ctr_rfc }, }; @@ -5562,7 +5567,7 @@ index 9033088c..ce9f4334 100644 /* From NIST Special Publication 800-38A, Appendix F.5 */ { .key = "\x2b\x7e\x15\x16\x28\xae\xd2\xa6" -@@ -20867,7 +20964,7 @@ static struct cipher_testvec aes_ofb_enc_tv_template[] = { +@@ -20867,7 +20964,7 @@ static struct cipher_testvec aes_ofb_enc } }; @@ -5571,7 +5576,7 @@ index 9033088c..ce9f4334 100644 /* From NIST Special Publication 800-38A, Appendix F.5 */ { .key = "\x2b\x7e\x15\x16\x28\xae\xd2\xa6" -@@ -20896,7 +20993,7 @@ static struct cipher_testvec aes_ofb_dec_tv_template[] = { +@@ -20896,7 +20993,7 @@ static struct cipher_testvec aes_ofb_dec } }; @@ -5580,7 +5585,7 @@ index 9033088c..ce9f4334 100644 { /* From McGrew & Viega - http://citeseer.ist.psu.edu/656989.html */ .key = zeroed_string, .klen = 16, -@@ -21056,7 +21153,7 @@ static struct aead_testvec aes_gcm_enc_tv_template[] = { +@@ -21056,7 +21153,7 @@ static struct aead_testvec aes_gcm_enc_t } }; @@ -5589,7 +5594,7 @@ index 9033088c..ce9f4334 100644 { /* From McGrew & Viega - http://citeseer.ist.psu.edu/656989.html */ .key = zeroed_string, .klen = 32, -@@ -21258,7 +21355,7 @@ static struct aead_testvec aes_gcm_dec_tv_template[] = { +@@ -21258,7 +21355,7 @@ static struct aead_testvec aes_gcm_dec_t } }; @@ -5598,7 +5603,7 @@ index 9033088c..ce9f4334 100644 { /* Generated using Crypto++ */ .key = zeroed_string, .klen = 20, -@@ -21871,7 +21968,7 @@ static struct aead_testvec aes_gcm_rfc4106_enc_tv_template[] = { +@@ -21871,7 +21968,7 @@ static struct aead_testvec aes_gcm_rfc41 } }; @@ -5607,7 +5612,7 @@ index 9033088c..ce9f4334 100644 { /* Generated using Crypto++ */ .key = zeroed_string, .klen = 20, -@@ -22485,7 +22582,7 @@ static struct aead_testvec aes_gcm_rfc4106_dec_tv_template[] = { +@@ -22485,7 +22582,7 @@ static struct aead_testvec aes_gcm_rfc41 } }; @@ -5616,7 +5621,7 @@ index 9033088c..ce9f4334 100644 { /* From draft-mcgrew-gcm-test-01 */ .key = "\x4c\x80\xcd\xef\xbb\x5d\x10\xda" "\x90\x6a\xc7\x3c\x36\x13\xa6\x34" -@@ -22516,7 +22613,7 @@ static struct aead_testvec aes_gcm_rfc4543_enc_tv_template[] = { +@@ -22516,7 +22613,7 @@ static struct aead_testvec aes_gcm_rfc45 } }; @@ -5625,7 +5630,7 @@ index 9033088c..ce9f4334 100644 { /* From draft-mcgrew-gcm-test-01 */ .key = "\x4c\x80\xcd\xef\xbb\x5d\x10\xda" "\x90\x6a\xc7\x3c\x36\x13\xa6\x34" -@@ -22575,7 +22672,7 @@ static struct aead_testvec aes_gcm_rfc4543_dec_tv_template[] = { +@@ -22575,7 +22672,7 @@ static struct aead_testvec aes_gcm_rfc45 }, }; @@ -5634,7 +5639,7 @@ index 9033088c..ce9f4334 100644 { /* From RFC 3610 */ .key = "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7" "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf", -@@ -22859,7 +22956,7 @@ static struct aead_testvec aes_ccm_enc_tv_template[] = { +@@ -22859,7 +22956,7 @@ static struct aead_testvec aes_ccm_enc_t } }; @@ -5643,7 +5648,7 @@ index 9033088c..ce9f4334 100644 { /* From RFC 3610 */ .key = "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7" "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf", -@@ -23191,7 +23288,7 @@ static struct aead_testvec aes_ccm_dec_tv_template[] = { +@@ -23191,7 +23288,7 @@ static struct aead_testvec aes_ccm_dec_t * These vectors are copied/generated from the ones for rfc4106 with * the key truncated by one byte.. */ @@ -5652,7 +5657,7 @@ index 9033088c..ce9f4334 100644 { /* Generated using Crypto++ */ .key = zeroed_string, .klen = 19, -@@ -23804,7 +23901,7 @@ static struct aead_testvec aes_ccm_rfc4309_enc_tv_template[] = { +@@ -23804,7 +23901,7 @@ static struct aead_testvec aes_ccm_rfc43 } }; @@ -5661,7 +5666,7 @@ index 9033088c..ce9f4334 100644 { /* Generated using Crypto++ */ .key = zeroed_string, .klen = 19, -@@ -24420,9 +24517,7 @@ static struct aead_testvec aes_ccm_rfc4309_dec_tv_template[] = { +@@ -24420,9 +24517,7 @@ static struct aead_testvec aes_ccm_rfc43 /* * ChaCha20-Poly1305 AEAD test vectors from RFC7539 2.8.2./A.5. */ @@ -5672,7 +5677,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x80\x81\x82\x83\x84\x85\x86\x87" "\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f" -@@ -24554,7 +24649,7 @@ static struct aead_testvec rfc7539_enc_tv_template[] = { +@@ -24554,7 +24649,7 @@ static struct aead_testvec rfc7539_enc_t }, }; @@ -5681,7 +5686,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x80\x81\x82\x83\x84\x85\x86\x87" "\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f" -@@ -24689,9 +24784,7 @@ static struct aead_testvec rfc7539_dec_tv_template[] = { +@@ -24689,9 +24784,7 @@ static struct aead_testvec rfc7539_dec_t /* * draft-irtf-cfrg-chacha20-poly1305 */ @@ -5692,7 +5697,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x1c\x92\x40\xa5\xeb\x55\xd3\x8a" "\xf3\x33\x88\x86\x04\xf6\xb5\xf0" -@@ -24779,7 +24872,7 @@ static struct aead_testvec rfc7539esp_enc_tv_template[] = { +@@ -24779,7 +24872,7 @@ static struct aead_testvec rfc7539esp_en }, }; @@ -5701,7 +5706,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x1c\x92\x40\xa5\xeb\x55\xd3\x8a" "\xf3\x33\x88\x86\x04\xf6\xb5\xf0" -@@ -24875,7 +24968,7 @@ static struct aead_testvec rfc7539esp_dec_tv_template[] = { +@@ -24875,7 +24968,7 @@ static struct aead_testvec rfc7539esp_de * semiblock of the ciphertext from the test vector. For decryption, iv is * the first semiblock of the ciphertext. */ @@ -5710,7 +5715,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x75\x75\xda\x3a\x93\x60\x7c\xc2" "\xbf\xd8\xce\xc7\xaa\xdf\xd9\xa6", -@@ -24890,7 +24983,7 @@ static struct cipher_testvec aes_kw_enc_tv_template[] = { +@@ -24890,7 +24983,7 @@ static struct cipher_testvec aes_kw_enc_ }, }; @@ -5719,7 +5724,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x80\xaa\x99\x73\x27\xa4\x80\x6b" "\x6a\x7a\x41\xa5\x2b\x86\xc3\x71" -@@ -24913,9 +25006,7 @@ static struct cipher_testvec aes_kw_dec_tv_template[] = { +@@ -24913,9 +25006,7 @@ static struct cipher_testvec aes_kw_dec_ * http://csrc.nist.gov/groups/STM/cavp/documents/rng/RNGVS.pdf * Only AES-128 is supported at this time. */ @@ -5730,7 +5735,7 @@ index 9033088c..ce9f4334 100644 { .key = "\xf3\xb1\x66\x6d\x13\x60\x72\x42" "\xed\x06\x1c\xab\xb8\xd4\x62\x02", -@@ -25011,7 +25102,7 @@ static struct cprng_testvec ansi_cprng_aes_tv_template[] = { +@@ -25011,7 +25102,7 @@ static struct cprng_testvec ansi_cprng_a * (Hash, HMAC, CTR) are tested with all permutations of use cases (w/ and * w/o personalization string, w/ and w/o additional input string). */ @@ -5739,7 +5744,7 @@ index 9033088c..ce9f4334 100644 { .entropy = (unsigned char *) "\x72\x88\x4c\xcd\x6c\x85\x57\x70\xf7\x0b\x8b\x86" -@@ -25169,7 +25260,7 @@ static struct drbg_testvec drbg_pr_sha256_tv_template[] = { +@@ -25169,7 +25260,7 @@ static struct drbg_testvec drbg_pr_sha25 }, }; @@ -5748,7 +5753,7 @@ index 9033088c..ce9f4334 100644 { .entropy = (unsigned char *) "\x99\x69\xe5\x4b\x47\x03\xff\x31\x78\x5b\x87\x9a" -@@ -25327,7 +25418,7 @@ static struct drbg_testvec drbg_pr_hmac_sha256_tv_template[] = { +@@ -25327,7 +25418,7 @@ static struct drbg_testvec drbg_pr_hmac_ }, }; @@ -5757,7 +5762,7 @@ index 9033088c..ce9f4334 100644 { .entropy = (unsigned char *) "\xd1\x44\xc6\x61\x81\x6d\xca\x9d\x15\x28\x8a\x42" -@@ -25451,7 +25542,7 @@ static struct drbg_testvec drbg_pr_ctr_aes128_tv_template[] = { +@@ -25451,7 +25542,7 @@ static struct drbg_testvec drbg_pr_ctr_a * (Hash, HMAC, CTR) are tested with all permutations of use cases (w/ and * w/o personalization string, w/ and w/o additional input string). */ @@ -5766,7 +5771,7 @@ index 9033088c..ce9f4334 100644 { .entropy = (unsigned char *) "\xa6\x5a\xd0\xf3\x45\xdb\x4e\x0e\xff\xe8\x75\xc3" -@@ -25573,7 +25664,7 @@ static struct drbg_testvec drbg_nopr_sha256_tv_template[] = { +@@ -25573,7 +25664,7 @@ static struct drbg_testvec drbg_nopr_sha }, }; @@ -5775,7 +5780,7 @@ index 9033088c..ce9f4334 100644 { .entropy = (unsigned char *) "\xca\x85\x19\x11\x34\x93\x84\xbf\xfe\x89\xde\x1c" -@@ -25695,7 +25786,7 @@ static struct drbg_testvec drbg_nopr_hmac_sha256_tv_template[] = { +@@ -25695,7 +25786,7 @@ static struct drbg_testvec drbg_nopr_hma }, }; @@ -5784,7 +5789,7 @@ index 9033088c..ce9f4334 100644 { .entropy = (unsigned char *) "\xc3\x5c\x2f\xa2\xa8\x9d\x52\xa1\x1f\xa3\x2a\xa9" -@@ -25719,7 +25810,7 @@ static struct drbg_testvec drbg_nopr_ctr_aes192_tv_template[] = { +@@ -25719,7 +25810,7 @@ static struct drbg_testvec drbg_nopr_ctr }, }; @@ -5793,7 +5798,7 @@ index 9033088c..ce9f4334 100644 { .entropy = (unsigned char *) "\x36\x40\x19\x40\xfa\x8b\x1f\xba\x91\xa1\x66\x1f" -@@ -25743,7 +25834,7 @@ static struct drbg_testvec drbg_nopr_ctr_aes256_tv_template[] = { +@@ -25743,7 +25834,7 @@ static struct drbg_testvec drbg_nopr_ctr }, }; @@ -5802,7 +5807,7 @@ index 9033088c..ce9f4334 100644 { .entropy = (unsigned char *) "\x87\xe1\xc5\x32\x99\x7f\x57\xa3\x5c\x28\x6d\xe8" -@@ -25832,14 +25923,7 @@ static struct drbg_testvec drbg_nopr_ctr_aes128_tv_template[] = { +@@ -25832,14 +25923,7 @@ static struct drbg_testvec drbg_nopr_ctr }; /* Cast5 test vectors from RFC 2144 */ @@ -5818,7 +5823,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x01\x23\x45\x67\x12\x34\x56\x78" "\x23\x45\x67\x89\x34\x56\x78\x9a", -@@ -26000,7 +26084,7 @@ static struct cipher_testvec cast5_enc_tv_template[] = { +@@ -26000,7 +26084,7 @@ static struct cipher_testvec cast5_enc_t }, }; @@ -5827,7 +5832,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x01\x23\x45\x67\x12\x34\x56\x78" "\x23\x45\x67\x89\x34\x56\x78\x9a", -@@ -26161,7 +26245,7 @@ static struct cipher_testvec cast5_dec_tv_template[] = { +@@ -26161,7 +26245,7 @@ static struct cipher_testvec cast5_dec_t }, }; @@ -5836,7 +5841,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from TF test vectors */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A", -@@ -26299,7 +26383,7 @@ static struct cipher_testvec cast5_cbc_enc_tv_template[] = { +@@ -26299,7 +26383,7 @@ static struct cipher_testvec cast5_cbc_e }, }; @@ -5845,7 +5850,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from TF test vectors */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A", -@@ -26437,7 +26521,7 @@ static struct cipher_testvec cast5_cbc_dec_tv_template[] = { +@@ -26437,7 +26521,7 @@ static struct cipher_testvec cast5_cbc_d }, }; @@ -5854,7 +5859,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from TF test vectors */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A", -@@ -26588,7 +26672,7 @@ static struct cipher_testvec cast5_ctr_enc_tv_template[] = { +@@ -26588,7 +26672,7 @@ static struct cipher_testvec cast5_ctr_e }, }; @@ -5863,7 +5868,7 @@ index 9033088c..ce9f4334 100644 { /* Generated from TF test vectors */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A", -@@ -26742,10 +26826,7 @@ static struct cipher_testvec cast5_ctr_dec_tv_template[] = { +@@ -26742,10 +26826,7 @@ static struct cipher_testvec cast5_ctr_d /* * ARC4 test vectors from OpenSSL */ @@ -5875,7 +5880,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x01\x23\x45\x67\x89\xab\xcd\xef", .klen = 8, -@@ -26811,7 +26892,7 @@ static struct cipher_testvec arc4_enc_tv_template[] = { +@@ -26811,7 +26892,7 @@ static struct cipher_testvec arc4_enc_tv }, }; @@ -5884,7 +5889,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x01\x23\x45\x67\x89\xab\xcd\xef", .klen = 8, -@@ -26880,10 +26961,7 @@ static struct cipher_testvec arc4_dec_tv_template[] = { +@@ -26880,10 +26961,7 @@ static struct cipher_testvec arc4_dec_tv /* * TEA test vectors */ @@ -5896,7 +5901,7 @@ index 9033088c..ce9f4334 100644 { .key = zeroed_string, .klen = 16, -@@ -26926,7 +27004,7 @@ static struct cipher_testvec tea_enc_tv_template[] = { +@@ -26926,7 +27004,7 @@ static struct cipher_testvec tea_enc_tv_ } }; @@ -5905,7 +5910,7 @@ index 9033088c..ce9f4334 100644 { .key = zeroed_string, .klen = 16, -@@ -26972,10 +27050,7 @@ static struct cipher_testvec tea_dec_tv_template[] = { +@@ -26972,10 +27050,7 @@ static struct cipher_testvec tea_dec_tv_ /* * XTEA test vectors */ @@ -5917,7 +5922,7 @@ index 9033088c..ce9f4334 100644 { .key = zeroed_string, .klen = 16, -@@ -27018,7 +27093,7 @@ static struct cipher_testvec xtea_enc_tv_template[] = { +@@ -27018,7 +27093,7 @@ static struct cipher_testvec xtea_enc_tv } }; @@ -5926,7 +5931,7 @@ index 9033088c..ce9f4334 100644 { .key = zeroed_string, .klen = 16, -@@ -27064,10 +27139,7 @@ static struct cipher_testvec xtea_dec_tv_template[] = { +@@ -27064,10 +27139,7 @@ static struct cipher_testvec xtea_dec_tv /* * KHAZAD test vectors. */ @@ -5938,7 +5943,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x80\x00\x00\x00\x00\x00\x00\x00" "\x00\x00\x00\x00\x00\x00\x00\x00", -@@ -27113,7 +27185,7 @@ static struct cipher_testvec khazad_enc_tv_template[] = { +@@ -27113,7 +27185,7 @@ static struct cipher_testvec khazad_enc_ }, }; @@ -5947,7 +5952,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x80\x00\x00\x00\x00\x00\x00\x00" "\x00\x00\x00\x00\x00\x00\x00\x00", -@@ -27163,12 +27235,7 @@ static struct cipher_testvec khazad_dec_tv_template[] = { +@@ -27163,12 +27235,7 @@ static struct cipher_testvec khazad_dec_ * Anubis test vectors. */ @@ -5961,7 +5966,7 @@ index 9033088c..ce9f4334 100644 { .key = "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe" "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe", -@@ -27231,7 +27298,7 @@ static struct cipher_testvec anubis_enc_tv_template[] = { +@@ -27231,7 +27298,7 @@ static struct cipher_testvec anubis_enc_ }, }; @@ -5970,7 +5975,7 @@ index 9033088c..ce9f4334 100644 { .key = "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe" "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe", -@@ -27294,7 +27361,7 @@ static struct cipher_testvec anubis_dec_tv_template[] = { +@@ -27294,7 +27361,7 @@ static struct cipher_testvec anubis_dec_ }, }; @@ -5979,7 +5984,7 @@ index 9033088c..ce9f4334 100644 { .key = "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe" "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe", -@@ -27329,7 +27396,7 @@ static struct cipher_testvec anubis_cbc_enc_tv_template[] = { +@@ -27329,7 +27396,7 @@ static struct cipher_testvec anubis_cbc_ }, }; @@ -5988,7 +5993,7 @@ index 9033088c..ce9f4334 100644 { .key = "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe" "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe", -@@ -27367,10 +27434,7 @@ static struct cipher_testvec anubis_cbc_dec_tv_template[] = { +@@ -27367,10 +27434,7 @@ static struct cipher_testvec anubis_cbc_ /* * XETA test vectors */ @@ -6000,7 +6005,7 @@ index 9033088c..ce9f4334 100644 { .key = zeroed_string, .klen = 16, -@@ -27413,7 +27477,7 @@ static struct cipher_testvec xeta_enc_tv_template[] = { +@@ -27413,7 +27477,7 @@ static struct cipher_testvec xeta_enc_tv } }; @@ -6009,7 +6014,7 @@ index 9033088c..ce9f4334 100644 { .key = zeroed_string, .klen = 16, -@@ -27459,10 +27523,7 @@ static struct cipher_testvec xeta_dec_tv_template[] = { +@@ -27459,10 +27523,7 @@ static struct cipher_testvec xeta_dec_tv /* * FCrypt test vectors */ @@ -6021,7 +6026,7 @@ index 9033088c..ce9f4334 100644 { /* http://www.openafs.org/pipermail/openafs-devel/2000-December/005320.html */ .key = "\x00\x00\x00\x00\x00\x00\x00\x00", .klen = 8, -@@ -27523,7 +27584,7 @@ static struct cipher_testvec fcrypt_pcbc_enc_tv_template[] = { +@@ -27523,7 +27584,7 @@ static struct cipher_testvec fcrypt_pcbc } }; @@ -6030,7 +6035,7 @@ index 9033088c..ce9f4334 100644 { /* http://www.openafs.org/pipermail/openafs-devel/2000-December/005320.html */ .key = "\x00\x00\x00\x00\x00\x00\x00\x00", .klen = 8, -@@ -27587,18 +27648,7 @@ static struct cipher_testvec fcrypt_pcbc_dec_tv_template[] = { +@@ -27587,18 +27648,7 @@ static struct cipher_testvec fcrypt_pcbc /* * CAMELLIA test vectors. */ @@ -6050,7 +6055,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x01\x23\x45\x67\x89\xab\xcd\xef" "\xfe\xdc\xba\x98\x76\x54\x32\x10", -@@ -27898,7 +27948,7 @@ static struct cipher_testvec camellia_enc_tv_template[] = { +@@ -27898,7 +27948,7 @@ static struct cipher_testvec camellia_en }, }; @@ -6059,7 +6064,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x01\x23\x45\x67\x89\xab\xcd\xef" "\xfe\xdc\xba\x98\x76\x54\x32\x10", -@@ -28198,7 +28248,7 @@ static struct cipher_testvec camellia_dec_tv_template[] = { +@@ -28198,7 +28248,7 @@ static struct cipher_testvec camellia_de }, }; @@ -6068,7 +6073,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x06\xa9\x21\x40\x36\xb8\xa1\x5b" "\x51\x2e\x03\xd5\x34\x12\x00\x06", -@@ -28494,7 +28544,7 @@ static struct cipher_testvec camellia_cbc_enc_tv_template[] = { +@@ -28494,7 +28544,7 @@ static struct cipher_testvec camellia_cb }, }; @@ -6077,7 +6082,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x06\xa9\x21\x40\x36\xb8\xa1\x5b" "\x51\x2e\x03\xd5\x34\x12\x00\x06", -@@ -28790,7 +28840,7 @@ static struct cipher_testvec camellia_cbc_dec_tv_template[] = { +@@ -28790,7 +28840,7 @@ static struct cipher_testvec camellia_cb }, }; @@ -6086,7 +6091,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -29457,7 +29507,7 @@ static struct cipher_testvec camellia_ctr_enc_tv_template[] = { +@@ -29457,7 +29507,7 @@ static struct cipher_testvec camellia_ct }, }; @@ -6095,7 +6100,7 @@ index 9033088c..ce9f4334 100644 { /* Generated with Crypto++ */ .key = "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9" "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A" -@@ -30124,7 +30174,7 @@ static struct cipher_testvec camellia_ctr_dec_tv_template[] = { +@@ -30124,7 +30174,7 @@ static struct cipher_testvec camellia_ct }, }; @@ -6104,7 +6109,7 @@ index 9033088c..ce9f4334 100644 /* Generated from AES-LRW test vectors */ { .key = "\x45\x62\xac\x25\xf8\x28\x17\x6d" -@@ -30376,7 +30426,7 @@ static struct cipher_testvec camellia_lrw_enc_tv_template[] = { +@@ -30376,7 +30426,7 @@ static struct cipher_testvec camellia_lr }, }; @@ -6113,7 +6118,7 @@ index 9033088c..ce9f4334 100644 /* Generated from AES-LRW test vectors */ /* same as enc vectors with input and result reversed */ { -@@ -30629,7 +30679,7 @@ static struct cipher_testvec camellia_lrw_dec_tv_template[] = { +@@ -30629,7 +30679,7 @@ static struct cipher_testvec camellia_lr }, }; @@ -6122,7 +6127,7 @@ index 9033088c..ce9f4334 100644 /* Generated from AES-XTS test vectors */ { .key = "\x00\x00\x00\x00\x00\x00\x00\x00" -@@ -30971,7 +31021,7 @@ static struct cipher_testvec camellia_xts_enc_tv_template[] = { +@@ -30971,7 +31021,7 @@ static struct cipher_testvec camellia_xt }, }; @@ -6131,7 +6136,7 @@ index 9033088c..ce9f4334 100644 /* Generated from AES-XTS test vectors */ /* same as enc vectors with input and result reversed */ { -@@ -31317,10 +31367,7 @@ static struct cipher_testvec camellia_xts_dec_tv_template[] = { +@@ -31317,10 +31367,7 @@ static struct cipher_testvec camellia_xt /* * SEED test vectors */ @@ -6143,7 +6148,7 @@ index 9033088c..ce9f4334 100644 { .key = zeroed_string, .klen = 16, -@@ -31362,7 +31409,7 @@ static struct cipher_testvec seed_enc_tv_template[] = { +@@ -31362,7 +31409,7 @@ static struct cipher_testvec seed_enc_tv } }; @@ -6152,7 +6157,7 @@ index 9033088c..ce9f4334 100644 { .key = zeroed_string, .klen = 16, -@@ -31404,8 +31451,7 @@ static struct cipher_testvec seed_dec_tv_template[] = { +@@ -31404,8 +31451,7 @@ static struct cipher_testvec seed_dec_tv } }; @@ -6162,7 +6167,7 @@ index 9033088c..ce9f4334 100644 /* * Testvectors from verified.test-vectors submitted to ECRYPT. * They are truncated to size 39, 64, 111, 129 to test a variety -@@ -32574,8 +32620,7 @@ static struct cipher_testvec salsa20_stream_enc_tv_template[] = { +@@ -32574,8 +32620,7 @@ static struct cipher_testvec salsa20_str }, }; @@ -6172,7 +6177,7 @@ index 9033088c..ce9f4334 100644 { /* RFC7539 A.2. Test Vector #1 */ .key = "\x00\x00\x00\x00\x00\x00\x00\x00" "\x00\x00\x00\x00\x00\x00\x00\x00" -@@ -33086,9 +33131,7 @@ static struct cipher_testvec chacha20_enc_tv_template[] = { +@@ -33086,9 +33131,7 @@ static struct cipher_testvec chacha20_en /* * CTS (Cipher Text Stealing) mode tests */ @@ -6183,7 +6188,7 @@ index 9033088c..ce9f4334 100644 { /* from rfc3962 */ .klen = 16, .key = "\x63\x68\x69\x63\x6b\x65\x6e\x20" -@@ -33190,7 +33233,7 @@ static struct cipher_testvec cts_mode_enc_tv_template[] = { +@@ -33190,7 +33233,7 @@ static struct cipher_testvec cts_mode_en } }; @@ -6204,7 +6209,7 @@ index 9033088c..ce9f4334 100644 { .inlen = 70, .outlen = 38, -@@ -33347,7 +33387,7 @@ static struct comp_testvec deflate_comp_tv_template[] = { +@@ -33347,7 +33387,7 @@ static struct comp_testvec deflate_comp_ }, }; @@ -6213,7 +6218,7 @@ index 9033088c..ce9f4334 100644 { .inlen = 122, .outlen = 191, -@@ -33386,10 +33426,7 @@ static struct comp_testvec deflate_decomp_tv_template[] = { +@@ -33386,10 +33426,7 @@ static struct comp_testvec deflate_decom /* * LZO test vectors (null-terminated strings). */ @@ -6225,7 +6230,7 @@ index 9033088c..ce9f4334 100644 { .inlen = 70, .outlen = 57, -@@ -33429,7 +33466,7 @@ static struct comp_testvec lzo_comp_tv_template[] = { +@@ -33429,7 +33466,7 @@ static struct comp_testvec lzo_comp_tv_t }, }; @@ -6234,7 +6239,7 @@ index 9033088c..ce9f4334 100644 { .inlen = 133, .outlen = 159, -@@ -33472,7 +33509,7 @@ static struct comp_testvec lzo_decomp_tv_template[] = { +@@ -33472,7 +33509,7 @@ static struct comp_testvec lzo_decomp_tv */ #define MICHAEL_MIC_TEST_VECTORS 6 @@ -6243,7 +6248,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x00\x00\x00\x00\x00\x00\x00\x00", .ksize = 8, -@@ -33520,9 +33557,7 @@ static struct hash_testvec michael_mic_tv_template[] = { +@@ -33520,9 +33557,7 @@ static struct hash_testvec michael_mic_t /* * CRC32 test vectors */ @@ -6254,7 +6259,7 @@ index 9033088c..ce9f4334 100644 { .key = "\x87\xa9\xcb\xed", .ksize = 4, -@@ -33954,9 +33989,7 @@ static struct hash_testvec crc32_tv_template[] = { +@@ -33954,9 +33989,7 @@ static struct hash_testvec crc32_tv_temp /* * CRC32C test vectors */ @@ -6265,7 +6270,7 @@ index 9033088c..ce9f4334 100644 { .psize = 0, .digest = "\x00\x00\x00\x00", -@@ -34392,9 +34425,7 @@ static struct hash_testvec crc32c_tv_template[] = { +@@ -34392,9 +34425,7 @@ static struct hash_testvec crc32c_tv_tem /* * Blakcifn CRC test vectors */ @@ -6276,7 +6281,7 @@ index 9033088c..ce9f4334 100644 { .psize = 0, .digest = "\x00\x00\x00\x00", -@@ -34479,9 +34510,6 @@ static struct hash_testvec bfin_crc_tv_template[] = { +@@ -34479,9 +34510,6 @@ static struct hash_testvec bfin_crc_tv_t }; @@ -6286,7 +6291,7 @@ index 9033088c..ce9f4334 100644 static struct comp_testvec lz4_comp_tv_template[] = { { .inlen = 70, -@@ -34512,9 +34540,6 @@ static struct comp_testvec lz4_decomp_tv_template[] = { +@@ -34512,9 +34540,6 @@ static struct comp_testvec lz4_decomp_tv }, }; @@ -6296,9 +6301,6 @@ index 9033088c..ce9f4334 100644 static struct comp_testvec lz4hc_comp_tv_template[] = { { .inlen = 70, -diff --git a/crypto/tls.c b/crypto/tls.c -new file mode 100644 -index 00000000..377226f5 --- /dev/null +++ b/crypto/tls.c @@ -0,0 +1,607 @@ @@ -6909,8 +6911,6 @@ index 00000000..377226f5 + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("TLS 1.0 record encryption"); -diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig -index 64bf3024..3831a6f7 100644 --- a/drivers/crypto/caam/Kconfig +++ b/drivers/crypto/caam/Kconfig @@ -1,6 +1,11 @@ @@ -6964,7 +6964,7 @@ index 64bf3024..3831a6f7 100644 help Enable the Job Ring's interrupt coalescing feature. -@@ -74,7 +86,6 @@ config CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD +@@ -74,7 +86,6 @@ config CRYPTO_DEV_FSL_CAAM_INTC_TIME_THL config CRYPTO_DEV_FSL_CAAM_CRYPTO_API tristate "Register algorithm implementations with the Crypto API" @@ -7015,7 +7015,7 @@ index 64bf3024..3831a6f7 100644 default y select CRYPTO_RNG select HW_RANDOM -@@ -124,13 +149,26 @@ config CRYPTO_DEV_FSL_CAAM_RNG_API +@@ -124,13 +149,31 @@ config CRYPTO_DEV_FSL_CAAM_RNG_API To compile this as a module, choose M here: the module will be called caamrng. @@ -7039,6 +7039,7 @@ index 64bf3024..3831a6f7 100644 + select CRYPTO_BLKCIPHER + select CRYPTO_AUTHENC + select CRYPTO_AEAD ++ select CRYPTO_HASH + ---help--- + CAAM driver for QorIQ Data Path Acceleration Architecture 2. + It handles DPSECI DPAA2 objects that sit on the Management Complex @@ -7051,11 +7052,13 @@ index 64bf3024..3831a6f7 100644 + def_tristate (CRYPTO_DEV_FSL_CAAM_CRYPTO_API || \ + CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI || \ + CRYPTO_DEV_FSL_DPAA2_CAAM) -diff --git a/drivers/crypto/caam/Makefile b/drivers/crypto/caam/Makefile -index 08bf5515..01f73a25 100644 ++ ++config CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC ++ def_tristate (CRYPTO_DEV_FSL_CAAM_AHASH_API || \ ++ CRYPTO_DEV_FSL_DPAA2_CAAM) --- a/drivers/crypto/caam/Makefile +++ b/drivers/crypto/caam/Makefile -@@ -5,13 +5,26 @@ ifeq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG), y) +@@ -5,13 +5,27 @@ ifeq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG ccflags-y := -DDEBUG endif @@ -7068,6 +7071,7 @@ index 08bf5515..01f73a25 100644 +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += caamalg_qi.o +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC) += caamalg_desc.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o ++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC) += caamhash_desc.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API) += caam_pkc.o @@ -7083,8 +7087,6 @@ index 08bf5515..01f73a25 100644 +obj-$(CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM) += dpaa2_caam.o + +dpaa2_caam-y := caamalg_qi2.o dpseci.o -diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c -index 0d743c63..6480a01f 100644 --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c @@ -2,6 +2,7 @@ @@ -7198,7 +7200,7 @@ index 0d743c63..6480a01f 100644 bool rfc3686; bool geniv; }; -@@ -163,302 +96,67 @@ struct caam_aead_alg { +@@ -163,302 +96,70 @@ struct caam_aead_alg { bool registered; }; @@ -7340,6 +7342,7 @@ index 0d743c63..6480a01f 100644 struct device *jrdev = ctx->jrdev; - bool keys_fit_inline = false; - u32 *key_jump_cmd, *jump_cmd, *read_move_cmd, *write_move_cmd; ++ struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent); u32 *desc; + int rem_bytes = CAAM_DESC_BYTES_MAX - AEAD_DESC_JOB_IO_LEN - + ctx->adata.keylen_pad; @@ -7426,7 +7429,8 @@ index 0d743c63..6480a01f 100644 - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); -#endif -+ cnstr_shdsc_aead_null_encap(desc, &ctx->adata, ctx->authsize); ++ cnstr_shdsc_aead_null_encap(desc, &ctx->adata, ctx->authsize, ++ ctrlpriv->era); + dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma, + desc_bytes(desc), DMA_TO_DEVICE); @@ -7522,18 +7526,20 @@ index 0d743c63..6480a01f 100644 - desc_bytes(desc), 1); -#endif + desc = ctx->sh_desc_dec; -+ cnstr_shdsc_aead_null_decap(desc, &ctx->adata, ctx->authsize); ++ cnstr_shdsc_aead_null_decap(desc, &ctx->adata, ctx->authsize, ++ ctrlpriv->era); + dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma, + desc_bytes(desc), DMA_TO_DEVICE); return 0; } -@@ -470,11 +168,11 @@ static int aead_set_sh_desc(struct crypto_aead *aead) +@@ -470,11 +171,12 @@ static int aead_set_sh_desc(struct crypt unsigned int ivsize = crypto_aead_ivsize(aead); struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; - bool keys_fit_inline; - u32 geniv, moveiv; ++ struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent); u32 ctx1_iv_off = 0; - u32 *desc; - const bool ctr_mode = ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == @@ -7544,7 +7550,7 @@ index 0d743c63..6480a01f 100644 OP_ALG_AAI_CTR_MOD128); const bool is_rfc3686 = alg->caam.rfc3686; -@@ -482,7 +180,7 @@ static int aead_set_sh_desc(struct crypto_aead *aead) +@@ -482,7 +184,7 @@ static int aead_set_sh_desc(struct crypt return 0; /* NULL encryption / decryption */ @@ -7553,7 +7559,7 @@ index 0d743c63..6480a01f 100644 return aead_null_set_sh_desc(aead); /* -@@ -497,8 +195,14 @@ static int aead_set_sh_desc(struct crypto_aead *aead) +@@ -497,8 +199,14 @@ static int aead_set_sh_desc(struct crypt * RFC3686 specific: * CONTEXT1[255:128] = {NONCE, IV, COUNTER} */ @@ -7569,7 +7575,7 @@ index 0d743c63..6480a01f 100644 if (alg->caam.geniv) goto skip_enc; -@@ -507,146 +211,64 @@ static int aead_set_sh_desc(struct crypto_aead *aead) +@@ -507,146 +215,64 @@ static int aead_set_sh_desc(struct crypt * Job Descriptor and Shared Descriptors * must all fit into the 64-word Descriptor h/w Buffer */ @@ -7589,33 +7595,31 @@ index 0d743c63..6480a01f 100644 - /* Class 2 operation */ - append_operation(desc, ctx->class2_alg_type | - OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); +- +- /* Read and write assoclen bytes */ +- append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ); +- append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ); + if (desc_inline_query(DESC_AEAD_ENC_LEN + + (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0), + AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask, + ARRAY_SIZE(data_len)) < 0) + return -EINVAL; -- /* Read and write assoclen bytes */ -- append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ); -- append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ); +- /* Skip assoc data */ +- append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF); + if (inl_mask & 1) + ctx->adata.key_virt = ctx->key; + else + ctx->adata.key_dma = ctx->key_dma; -- /* Skip assoc data */ -- append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF); +- /* read assoc before reading payload */ +- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG | +- FIFOLDST_VLF); + if (inl_mask & 2) + ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad; + else + ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; -- /* read assoc before reading payload */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG | -- FIFOLDST_VLF); -+ ctx->adata.key_inline = !!(inl_mask & 1); -+ ctx->cdata.key_inline = !!(inl_mask & 2); - - /* Load Counter into CONTEXT1 reg */ - if (is_rfc3686) - append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB | @@ -7635,7 +7639,9 @@ index 0d743c63..6480a01f 100644 - /* Write ICV */ - append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB | - LDST_SRCDST_BYTE_CONTEXT); -- ++ ctx->adata.key_inline = !!(inl_mask & 1); ++ ctx->cdata.key_inline = !!(inl_mask & 2); + - ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc, - desc_bytes(desc), - DMA_TO_DEVICE); @@ -7652,7 +7658,7 @@ index 0d743c63..6480a01f 100644 + desc = ctx->sh_desc_enc; + cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ivsize, + ctx->authsize, is_rfc3686, nonce, ctx1_iv_off, -+ false); ++ false, ctrlpriv->era); + dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma, + desc_bytes(desc), DMA_TO_DEVICE); @@ -7694,8 +7700,7 @@ index 0d743c63..6480a01f 100644 - - /* Skip assoc data */ - append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF); -+ ctx->adata.key_dma = ctx->key_dma; - +- - /* read assoc before reading payload */ - append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG | - KEY_VLF); @@ -7714,7 +7719,8 @@ index 0d743c63..6480a01f 100644 - LDST_SRCDST_BYTE_CONTEXT | - ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) << - LDST_OFFSET_SHIFT)); -- ++ ctx->adata.key_dma = ctx->key_dma; + - /* Choose operation */ - if (ctr_mode) - append_operation(desc, ctx->class1_alg_type | @@ -7729,13 +7735,13 @@ index 0d743c63..6480a01f 100644 - append_math_add(desc, VARSEQINLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ); - append_math_add(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ); - aead_append_src_dst(desc, FIFOLD_TYPE_MSG); -+ ctx->adata.key_inline = !!(inl_mask & 1); -+ ctx->cdata.key_inline = !!(inl_mask & 2); - +- - /* Load ICV */ - append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS2 | - FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV); -- ++ ctx->adata.key_inline = !!(inl_mask & 1); ++ ctx->cdata.key_inline = !!(inl_mask & 2); + - ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc, - desc_bytes(desc), - DMA_TO_DEVICE); @@ -7752,13 +7758,13 @@ index 0d743c63..6480a01f 100644 + desc = ctx->sh_desc_dec; + cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata, ivsize, + ctx->authsize, alg->caam.geniv, is_rfc3686, -+ nonce, ctx1_iv_off, false); ++ nonce, ctx1_iv_off, false, ctrlpriv->era); + dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma, + desc_bytes(desc), DMA_TO_DEVICE); if (!alg->caam.geniv) goto skip_givenc; -@@ -655,107 +277,32 @@ static int aead_set_sh_desc(struct crypto_aead *aead) +@@ -655,107 +281,32 @@ skip_enc: * Job Descriptor and Shared Descriptors * must all fit into the 64-word Descriptor h/w Buffer */ @@ -7768,29 +7774,25 @@ index 0d743c63..6480a01f 100644 - (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0) <= - CAAM_DESC_BYTES_MAX) - keys_fit_inline = true; +- +- /* aead_givencrypt shared descriptor */ +- desc = ctx->sh_desc_enc; +- +- /* Note: Context registers are saved. */ +- init_sh_desc_key_aead(desc, ctx, keys_fit_inline, is_rfc3686); + if (desc_inline_query(DESC_AEAD_GIVENC_LEN + + (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0), + AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask, + ARRAY_SIZE(data_len)) < 0) + return -EINVAL; -- /* aead_givencrypt shared descriptor */ -- desc = ctx->sh_desc_enc; +- if (is_rfc3686) +- goto copy_iv; + if (inl_mask & 1) + ctx->adata.key_virt = ctx->key; + else + ctx->adata.key_dma = ctx->key_dma; -- /* Note: Context registers are saved. */ -- init_sh_desc_key_aead(desc, ctx, keys_fit_inline, is_rfc3686); -+ if (inl_mask & 2) -+ ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad; -+ else -+ ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; - -- if (is_rfc3686) -- goto copy_iv; -- - /* Generate IV */ - geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO | - NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 | @@ -7835,7 +7837,11 @@ index 0d743c63..6480a01f 100644 - LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM); - append_load_imm_u32(desc, ivsize, LDST_CLASS_2_CCB | - LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM); -- ++ if (inl_mask & 2) ++ ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad; ++ else ++ ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; + - /* Load Counter into CONTEXT1 reg */ - if (is_rfc3686) - append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB | @@ -7863,7 +7869,9 @@ index 0d743c63..6480a01f 100644 - /* Write ICV */ - append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB | - LDST_SRCDST_BYTE_CONTEXT); -- ++ ctx->adata.key_inline = !!(inl_mask & 1); ++ ctx->cdata.key_inline = !!(inl_mask & 2); + - ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc, - desc_bytes(desc), - DMA_TO_DEVICE); @@ -7876,20 +7884,17 @@ index 0d743c63..6480a01f 100644 - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); -#endif -+ ctx->adata.key_inline = !!(inl_mask & 1); -+ ctx->cdata.key_inline = !!(inl_mask & 2); -+ + /* aead_givencrypt shared descriptor */ + desc = ctx->sh_desc_enc; + cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata, ivsize, + ctx->authsize, is_rfc3686, nonce, -+ ctx1_iv_off, false); ++ ctx1_iv_off, false, ctrlpriv->era); + dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma, + desc_bytes(desc), DMA_TO_DEVICE); skip_givenc: return 0; -@@ -776,12 +323,12 @@ static int gcm_set_sh_desc(struct crypto_aead *aead) +@@ -776,12 +327,12 @@ static int gcm_set_sh_desc(struct crypto { struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; @@ -7906,7 +7911,7 @@ index 0d743c63..6480a01f 100644 return 0; /* -@@ -789,175 +336,35 @@ static int gcm_set_sh_desc(struct crypto_aead *aead) +@@ -789,175 +340,35 @@ static int gcm_set_sh_desc(struct crypto * Job Descriptor and Shared Descriptor * must fit into the 64-word Descriptor h/w Buffer */ @@ -8102,7 +8107,7 @@ index 0d743c63..6480a01f 100644 return 0; } -@@ -976,11 +383,12 @@ static int rfc4106_set_sh_desc(struct crypto_aead *aead) +@@ -976,11 +387,12 @@ static int rfc4106_set_sh_desc(struct cr { struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; @@ -8118,7 +8123,7 @@ index 0d743c63..6480a01f 100644 return 0; /* -@@ -988,148 +396,37 @@ static int rfc4106_set_sh_desc(struct crypto_aead *aead) +@@ -988,148 +400,37 @@ static int rfc4106_set_sh_desc(struct cr * Job Descriptor and Shared Descriptor * must fit into the 64-word Descriptor h/w Buffer */ @@ -8289,7 +8294,7 @@ index 0d743c63..6480a01f 100644 return 0; } -@@ -1149,12 +446,12 @@ static int rfc4543_set_sh_desc(struct crypto_aead *aead) +@@ -1149,12 +450,12 @@ static int rfc4543_set_sh_desc(struct cr { struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; @@ -8306,15 +8311,22 @@ index 0d743c63..6480a01f 100644 return 0; /* -@@ -1162,151 +459,37 @@ static int rfc4543_set_sh_desc(struct crypto_aead *aead) +@@ -1162,151 +463,37 @@ static int rfc4543_set_sh_desc(struct cr * Job Descriptor and Shared Descriptor * must fit into the 64-word Descriptor h/w Buffer */ - if (DESC_RFC4543_ENC_LEN + GCM_DESC_JOB_IO_LEN + - ctx->enckeylen <= CAAM_DESC_BYTES_MAX) - keys_fit_inline = true; -- -- desc = ctx->sh_desc_enc; ++ if (rem_bytes >= DESC_RFC4543_ENC_LEN) { ++ ctx->cdata.key_inline = true; ++ ctx->cdata.key_virt = ctx->key; ++ } else { ++ ctx->cdata.key_inline = false; ++ ctx->cdata.key_dma = ctx->key_dma; ++ } + + desc = ctx->sh_desc_enc; - - init_sh_desc(desc, HDR_SHARE_SERIAL); - @@ -8371,20 +8383,12 @@ index 0d743c63..6480a01f 100644 - if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) { - dev_err(jrdev, "unable to map shared descriptor\n"); - return -ENOMEM; -+ if (rem_bytes >= DESC_RFC4543_ENC_LEN) { -+ ctx->cdata.key_inline = true; -+ ctx->cdata.key_virt = ctx->key; -+ } else { -+ ctx->cdata.key_inline = false; -+ ctx->cdata.key_dma = ctx->key_dma; - } +- } -#ifdef DEBUG - print_hex_dump(KERN_ERR, "rfc4543 enc shdesc@"__stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); -#endif -+ -+ desc = ctx->sh_desc_enc; + cnstr_shdsc_rfc4543_encap(desc, &ctx->cdata, ivsize, ctx->authsize, + false); + dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma, @@ -8481,7 +8485,7 @@ index 0d743c63..6480a01f 100644 return 0; } -@@ -1322,19 +505,9 @@ static int rfc4543_setauthsize(struct crypto_aead *authenc, +@@ -1322,74 +509,67 @@ static int rfc4543_setauthsize(struct cr return 0; } @@ -8500,8 +8504,10 @@ index 0d743c63..6480a01f 100644 - static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 }; struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; ++ struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent); struct crypto_authenc_keys keys; -@@ -1343,53 +516,32 @@ static int aead_setkey(struct crypto_aead *aead, + int ret = 0; + if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) goto badkey; @@ -8524,6 +8530,27 @@ index 0d743c63..6480a01f 100644 #endif - ret = gen_split_aead_key(ctx, keys.authkey, keys.authkeylen); ++ /* ++ * If DKP is supported, use it in the shared descriptor to generate ++ * the split key. ++ */ ++ if (ctrlpriv->era >= 6) { ++ ctx->adata.keylen = keys.authkeylen; ++ ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & ++ OP_ALG_ALGSEL_MASK); ++ ++ if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE) ++ goto badkey; ++ ++ memcpy(ctx->key, keys.authkey, keys.authkeylen); ++ memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, ++ keys.enckeylen); ++ dma_sync_single_for_device(jrdev, ctx->key_dma, ++ ctx->adata.keylen_pad + ++ keys.enckeylen, DMA_TO_DEVICE); ++ goto skip_split_key; ++ } ++ + ret = gen_split_key(ctx->jrdev, ctx->key, &ctx->adata, keys.authkey, + keys.authkeylen, CAAM_MAX_KEY_SIZE - + keys.enckeylen); @@ -8549,7 +8576,7 @@ index 0d743c63..6480a01f 100644 - ctx->split_key_pad_len + keys.enckeylen, 1); + ctx->adata.keylen_pad + keys.enckeylen, 1); #endif -- + - ctx->enckeylen = keys.enckeylen; - - ret = aead_set_sh_desc(aead); @@ -8559,12 +8586,13 @@ index 0d743c63..6480a01f 100644 - } - - return ret; ++skip_split_key: + ctx->cdata.keylen = keys.enckeylen; + return aead_set_sh_desc(aead); badkey: crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN); return -EINVAL; -@@ -1400,7 +552,6 @@ static int gcm_setkey(struct crypto_aead *aead, +@@ -1400,7 +580,6 @@ static int gcm_setkey(struct crypto_aead { struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; @@ -8572,7 +8600,7 @@ index 0d743c63..6480a01f 100644 #ifdef DEBUG print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ", -@@ -1408,21 +559,10 @@ static int gcm_setkey(struct crypto_aead *aead, +@@ -1408,21 +587,10 @@ static int gcm_setkey(struct crypto_aead #endif memcpy(ctx->key, key, keylen); @@ -8583,21 +8611,21 @@ index 0d743c63..6480a01f 100644 - return -ENOMEM; - } - ctx->enckeylen = keylen; -- ++ dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, DMA_TO_DEVICE); ++ ctx->cdata.keylen = keylen; + - ret = gcm_set_sh_desc(aead); - if (ret) { - dma_unmap_single(jrdev, ctx->key_dma, ctx->enckeylen, - DMA_TO_DEVICE); - } -+ dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, DMA_TO_DEVICE); -+ ctx->cdata.keylen = keylen; - +- - return ret; + return gcm_set_sh_desc(aead); } static int rfc4106_setkey(struct crypto_aead *aead, -@@ -1430,7 +570,6 @@ static int rfc4106_setkey(struct crypto_aead *aead, +@@ -1430,7 +598,6 @@ static int rfc4106_setkey(struct crypto_ { struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; @@ -8605,7 +8633,7 @@ index 0d743c63..6480a01f 100644 if (keylen < 4) return -EINVAL; -@@ -1446,22 +585,10 @@ static int rfc4106_setkey(struct crypto_aead *aead, +@@ -1446,22 +613,10 @@ static int rfc4106_setkey(struct crypto_ * The last four bytes of the key material are used as the salt value * in the nonce. Update the AES key length. */ @@ -8632,7 +8660,7 @@ index 0d743c63..6480a01f 100644 } static int rfc4543_setkey(struct crypto_aead *aead, -@@ -1469,7 +596,6 @@ static int rfc4543_setkey(struct crypto_aead *aead, +@@ -1469,7 +624,6 @@ static int rfc4543_setkey(struct crypto_ { struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; @@ -8640,7 +8668,7 @@ index 0d743c63..6480a01f 100644 if (keylen < 4) return -EINVAL; -@@ -1485,43 +611,28 @@ static int rfc4543_setkey(struct crypto_aead *aead, +@@ -1485,43 +639,28 @@ static int rfc4543_setkey(struct crypto_ * The last four bytes of the key material are used as the salt value * in the nonce. Update the AES key length. */ @@ -8691,7 +8719,7 @@ index 0d743c63..6480a01f 100644 #ifdef DEBUG print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ", DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); -@@ -1544,215 +655,33 @@ static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher, +@@ -1544,215 +683,33 @@ static int ablkcipher_setkey(struct cryp keylen -= CTR_RFC3686_NONCE_SIZE; } @@ -8734,15 +8762,15 @@ index 0d743c63..6480a01f 100644 - } - - set_jump_tgt_here(desc, key_jump_cmd); +- +- /* Load iv */ +- append_seq_load(desc, crt->ivsize, LDST_SRCDST_BYTE_CONTEXT | +- LDST_CLASS_1_CCB | (ctx1_iv_off << LDST_OFFSET_SHIFT)); + cnstr_shdsc_ablkcipher_encap(desc, &ctx->cdata, ivsize, is_rfc3686, + ctx1_iv_off); + dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma, + desc_bytes(desc), DMA_TO_DEVICE); -- /* Load iv */ -- append_seq_load(desc, crt->ivsize, LDST_SRCDST_BYTE_CONTEXT | -- LDST_CLASS_1_CCB | (ctx1_iv_off << LDST_OFFSET_SHIFT)); -- - /* Load counter into CONTEXT1 reg */ - if (is_rfc3686) - append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB | @@ -8924,7 +8952,7 @@ index 0d743c63..6480a01f 100644 } static int xts_ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher, -@@ -1760,8 +689,7 @@ static int xts_ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher, +@@ -1760,8 +717,7 @@ static int xts_ablkcipher_setkey(struct { struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); struct device *jrdev = ctx->jrdev; @@ -8934,7 +8962,7 @@ index 0d743c63..6480a01f 100644 if (keylen != 2 * AES_MIN_KEY_SIZE && keylen != 2 * AES_MAX_KEY_SIZE) { crypto_ablkcipher_set_flags(ablkcipher, -@@ -1771,126 +699,38 @@ static int xts_ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher, +@@ -1771,126 +727,38 @@ static int xts_ablkcipher_setkey(struct } memcpy(ctx->key, key, keylen); @@ -9074,7 +9102,7 @@ index 0d743c63..6480a01f 100644 int sec4_sg_bytes; dma_addr_t sec4_sg_dma; struct sec4_sg_entry *sec4_sg; -@@ -1899,12 +739,12 @@ struct aead_edesc { +@@ -1899,12 +767,12 @@ struct aead_edesc { /* * ablkcipher_edesc - s/w-extended ablkcipher descriptor @@ -9090,7 +9118,7 @@ index 0d743c63..6480a01f 100644 * @hw_desc: the h/w job descriptor followed by any referenced link tables */ struct ablkcipher_edesc { -@@ -1924,10 +764,11 @@ static void caam_unmap(struct device *dev, struct scatterlist *src, +@@ -1924,10 +792,11 @@ static void caam_unmap(struct device *de int sec4_sg_bytes) { if (dst != src) { @@ -9105,7 +9133,7 @@ index 0d743c63..6480a01f 100644 } if (iv_dma) -@@ -2021,8 +862,7 @@ static void ablkcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err, +@@ -2021,8 +890,7 @@ static void ablkcipher_encrypt_done(stru dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); #endif @@ -9115,7 +9143,7 @@ index 0d743c63..6480a01f 100644 if (err) caam_jr_strstatus(jrdev, err); -@@ -2031,10 +871,10 @@ static void ablkcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err, +@@ -2031,10 +899,10 @@ static void ablkcipher_encrypt_done(stru print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ", DUMP_PREFIX_ADDRESS, 16, 4, req->info, edesc->src_nents > 1 ? 100 : ivsize, 1); @@ -9129,7 +9157,7 @@ index 0d743c63..6480a01f 100644 ablkcipher_unmap(jrdev, edesc, req); -@@ -2062,8 +902,7 @@ static void ablkcipher_decrypt_done(struct device *jrdev, u32 *desc, u32 err, +@@ -2062,8 +930,7 @@ static void ablkcipher_decrypt_done(stru dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); #endif @@ -9139,7 +9167,7 @@ index 0d743c63..6480a01f 100644 if (err) caam_jr_strstatus(jrdev, err); -@@ -2071,10 +910,10 @@ static void ablkcipher_decrypt_done(struct device *jrdev, u32 *desc, u32 err, +@@ -2071,10 +938,10 @@ static void ablkcipher_decrypt_done(stru print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ", DUMP_PREFIX_ADDRESS, 16, 4, req->info, ivsize, 1); @@ -9153,7 +9181,7 @@ index 0d743c63..6480a01f 100644 ablkcipher_unmap(jrdev, edesc, req); -@@ -2114,7 +953,7 @@ static void init_aead_job(struct aead_request *req, +@@ -2114,7 +981,7 @@ static void init_aead_job(struct aead_re init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE); if (all_contig) { @@ -9162,7 +9190,7 @@ index 0d743c63..6480a01f 100644 in_options = 0; } else { src_dma = edesc->sec4_sg_dma; -@@ -2129,7 +968,7 @@ static void init_aead_job(struct aead_request *req, +@@ -2129,7 +996,7 @@ static void init_aead_job(struct aead_re out_options = in_options; if (unlikely(req->src != req->dst)) { @@ -9171,7 +9199,25 @@ index 0d743c63..6480a01f 100644 dst_dma = sg_dma_address(req->dst); } else { dst_dma = edesc->sec4_sg_dma + -@@ -2175,7 +1014,7 @@ static void init_gcm_job(struct aead_request *req, +@@ -2147,9 +1014,6 @@ static void init_aead_job(struct aead_re + append_seq_out_ptr(desc, dst_dma, + req->assoclen + req->cryptlen - authsize, + out_options); +- +- /* REG3 = assoclen */ +- append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen); + } + + static void init_gcm_job(struct aead_request *req, +@@ -2164,6 +1028,7 @@ static void init_gcm_job(struct aead_req + unsigned int last; + + init_aead_job(req, edesc, all_contig, encrypt); ++ append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen); + + /* BUG This should not be specific to generic GCM. */ + last = 0; +@@ -2175,7 +1040,7 @@ static void init_gcm_job(struct aead_req FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | 12 | last); /* Append Salt */ if (!generic_gcm) @@ -9180,16 +9226,33 @@ index 0d743c63..6480a01f 100644 /* Append IV */ append_data(desc, req->iv, ivsize); /* End of blank commands */ -@@ -2190,7 +1029,7 @@ static void init_authenc_job(struct aead_request *req, +@@ -2190,7 +1055,8 @@ static void init_authenc_job(struct aead struct caam_aead_alg, aead); unsigned int ivsize = crypto_aead_ivsize(aead); struct caam_ctx *ctx = crypto_aead_ctx(aead); - const bool ctr_mode = ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == ++ struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent); + const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) == OP_ALG_AAI_CTR_MOD128); const bool is_rfc3686 = alg->caam.rfc3686; u32 *desc = edesc->hw_desc; -@@ -2236,16 +1075,15 @@ static void init_ablkcipher_job(u32 *sh_desc, dma_addr_t ptr, +@@ -2213,6 +1079,15 @@ static void init_authenc_job(struct aead + + init_aead_job(req, edesc, all_contig, encrypt); + ++ /* ++ * {REG3, DPOVRD} = assoclen, depending on whether MATH command supports ++ * having DPOVRD as destination. ++ */ ++ if (ctrlpriv->era < 3) ++ append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen); ++ else ++ append_math_add_imm_u32(desc, DPOVRD, ZERO, IMM, req->assoclen); ++ + if (ivsize && ((is_rfc3686 && encrypt) || !alg->caam.geniv)) + append_load_as_imm(desc, req->iv, ivsize, + LDST_CLASS_1_CCB | +@@ -2236,16 +1111,15 @@ static void init_ablkcipher_job(u32 *sh_ int len, sec4_sg_index = 0; #ifdef DEBUG @@ -9211,7 +9274,7 @@ index 0d743c63..6480a01f 100644 len = desc_len(sh_desc); init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE); -@@ -2261,7 +1099,7 @@ static void init_ablkcipher_job(u32 *sh_desc, dma_addr_t ptr, +@@ -2261,7 +1135,7 @@ static void init_ablkcipher_job(u32 *sh_ append_seq_in_ptr(desc, src_dma, req->nbytes + ivsize, in_options); if (likely(req->src == req->dst)) { @@ -9220,7 +9283,7 @@ index 0d743c63..6480a01f 100644 dst_dma = sg_dma_address(req->src); } else { dst_dma = edesc->sec4_sg_dma + -@@ -2269,7 +1107,7 @@ static void init_ablkcipher_job(u32 *sh_desc, dma_addr_t ptr, +@@ -2269,7 +1143,7 @@ static void init_ablkcipher_job(u32 *sh_ out_options = LDST_SGF; } } else { @@ -9229,7 +9292,7 @@ index 0d743c63..6480a01f 100644 dst_dma = sg_dma_address(req->dst); } else { dst_dma = edesc->sec4_sg_dma + -@@ -2296,20 +1134,18 @@ static void init_ablkcipher_giv_job(u32 *sh_desc, dma_addr_t ptr, +@@ -2296,20 +1170,18 @@ static void init_ablkcipher_giv_job(u32 int len, sec4_sg_index = 0; #ifdef DEBUG @@ -9254,7 +9317,7 @@ index 0d743c63..6480a01f 100644 src_dma = sg_dma_address(req->src); in_options = 0; } else { -@@ -2340,87 +1176,100 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req, +@@ -2340,87 +1212,100 @@ static struct aead_edesc *aead_edesc_all struct crypto_aead *aead = crypto_aead_reqtfm(req); struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; @@ -9410,7 +9473,7 @@ index 0d743c63..6480a01f 100644 edesc->sec4_sg + sec4_sg_index, 0); } -@@ -2573,13 +1422,9 @@ static int aead_decrypt(struct aead_request *req) +@@ -2573,13 +1458,9 @@ static int aead_decrypt(struct aead_requ u32 *desc; int ret = 0; @@ -9427,7 +9490,7 @@ index 0d743c63..6480a01f 100644 /* allocate extended descriptor */ edesc = aead_edesc_alloc(req, AUTHENC_DESC_JOB_IO_LEN, -@@ -2619,51 +1464,80 @@ static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request +@@ -2619,51 +1500,80 @@ static struct ablkcipher_edesc *ablkciph struct device *jrdev = ctx->jrdev; gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? GFP_KERNEL : GFP_ATOMIC; @@ -9531,7 +9594,7 @@ index 0d743c63..6480a01f 100644 return ERR_PTR(-ENOMEM); } -@@ -2673,23 +1547,24 @@ static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request +@@ -2673,23 +1583,24 @@ static struct ablkcipher_edesc *ablkciph edesc->sec4_sg = (void *)edesc + sizeof(struct ablkcipher_edesc) + desc_bytes; @@ -9563,7 +9626,7 @@ index 0d743c63..6480a01f 100644 return ERR_PTR(-ENOMEM); } -@@ -2701,7 +1576,7 @@ static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request +@@ -2701,7 +1612,7 @@ static struct ablkcipher_edesc *ablkciph sec4_sg_bytes, 1); #endif @@ -9572,7 +9635,7 @@ index 0d743c63..6480a01f 100644 return edesc; } -@@ -2792,30 +1667,54 @@ static struct ablkcipher_edesc *ablkcipher_giv_edesc_alloc( +@@ -2792,30 +1703,54 @@ static struct ablkcipher_edesc *ablkciph struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); struct device *jrdev = ctx->jrdev; @@ -9643,7 +9706,7 @@ index 0d743c63..6480a01f 100644 } /* -@@ -2825,21 +1724,29 @@ static struct ablkcipher_edesc *ablkcipher_giv_edesc_alloc( +@@ -2825,21 +1760,29 @@ static struct ablkcipher_edesc *ablkciph iv_dma = dma_map_single(jrdev, greq->giv, ivsize, DMA_TO_DEVICE); if (dma_mapping_error(jrdev, iv_dma)) { dev_err(jrdev, "unable to map IV\n"); @@ -9679,7 +9742,7 @@ index 0d743c63..6480a01f 100644 return ERR_PTR(-ENOMEM); } -@@ -2849,24 +1756,24 @@ static struct ablkcipher_edesc *ablkcipher_giv_edesc_alloc( +@@ -2849,24 +1792,24 @@ static struct ablkcipher_edesc *ablkciph edesc->sec4_sg = (void *)edesc + sizeof(struct ablkcipher_edesc) + desc_bytes; @@ -9714,7 +9777,7 @@ index 0d743c63..6480a01f 100644 return ERR_PTR(-ENOMEM); } edesc->iv_dma = iv_dma; -@@ -2878,7 +1785,7 @@ static struct ablkcipher_edesc *ablkcipher_giv_edesc_alloc( +@@ -2878,7 +1821,7 @@ static struct ablkcipher_edesc *ablkciph sec4_sg_bytes, 1); #endif @@ -9723,7 +9786,7 @@ index 0d743c63..6480a01f 100644 return edesc; } -@@ -2889,7 +1796,7 @@ static int ablkcipher_givencrypt(struct skcipher_givcrypt_request *creq) +@@ -2889,7 +1832,7 @@ static int ablkcipher_givencrypt(struct struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); struct device *jrdev = ctx->jrdev; @@ -9732,7 +9795,7 @@ index 0d743c63..6480a01f 100644 u32 *desc; int ret = 0; -@@ -2933,7 +1840,6 @@ struct caam_alg_template { +@@ -2933,7 +1876,6 @@ struct caam_alg_template { } template_u; u32 class1_alg_type; u32 class2_alg_type; @@ -9740,7 +9803,7 @@ index 0d743c63..6480a01f 100644 }; static struct caam_alg_template driver_algs[] = { -@@ -3118,7 +2024,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3118,7 +2060,6 @@ static struct caam_aead_alg driver_aeads .caam = { .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9748,7 +9811,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3140,7 +2045,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3140,7 +2081,6 @@ static struct caam_aead_alg driver_aeads .caam = { .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9756,7 +9819,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3162,7 +2066,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3162,7 +2102,6 @@ static struct caam_aead_alg driver_aeads .caam = { .class2_alg_type = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9764,7 +9827,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3184,7 +2087,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3184,7 +2123,6 @@ static struct caam_aead_alg driver_aeads .caam = { .class2_alg_type = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9772,7 +9835,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3206,7 +2108,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3206,7 +2144,6 @@ static struct caam_aead_alg driver_aeads .caam = { .class2_alg_type = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9780,7 +9843,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3228,7 +2129,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3228,7 +2165,6 @@ static struct caam_aead_alg driver_aeads .caam = { .class2_alg_type = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9788,7 +9851,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3250,7 +2150,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3250,7 +2186,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9796,7 +9859,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3273,7 +2172,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3273,7 +2208,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9804,7 +9867,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3296,7 +2194,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3296,7 +2230,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9812,7 +9875,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3319,7 +2216,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3319,7 +2252,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9820,7 +9883,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3342,7 +2238,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3342,7 +2274,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9828,7 +9891,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3365,7 +2260,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3365,7 +2296,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9836,7 +9899,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3388,7 +2282,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3388,7 +2318,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9844,7 +9907,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3411,7 +2304,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3411,7 +2340,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9852,7 +9915,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3434,7 +2326,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3434,7 +2362,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9860,7 +9923,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3457,7 +2348,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3457,7 +2384,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9868,7 +9931,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3480,7 +2370,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3480,7 +2406,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9876,7 +9939,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3503,7 +2392,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3503,7 +2428,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9884,7 +9947,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3526,7 +2414,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3526,7 +2450,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9892,7 +9955,7 @@ index 0d743c63..6480a01f 100644 } }, { -@@ -3549,7 +2436,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3549,7 +2472,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9900,7 +9963,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, } }, -@@ -3573,7 +2459,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3573,7 +2495,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9908,7 +9971,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3597,7 +2482,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3597,7 +2518,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9916,7 +9979,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3621,7 +2505,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3621,7 +2541,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9924,7 +9987,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3645,7 +2528,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3645,7 +2564,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9932,7 +9995,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3669,7 +2551,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3669,7 +2587,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9940,7 +10003,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3693,7 +2574,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3693,7 +2610,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9948,7 +10011,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3717,7 +2597,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3717,7 +2633,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9956,7 +10019,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3741,7 +2620,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3741,7 +2656,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9964,7 +10027,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3765,7 +2643,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3765,7 +2679,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9972,7 +10035,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3789,7 +2666,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3789,7 +2702,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9980,7 +10043,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3812,7 +2688,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3812,7 +2724,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9988,7 +10051,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3835,7 +2710,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3835,7 +2746,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP, @@ -9996,7 +10059,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3858,7 +2732,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3858,7 +2768,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10004,7 +10067,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3881,7 +2754,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3881,7 +2790,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10012,7 +10075,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3904,7 +2776,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3904,7 +2812,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10020,7 +10083,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3927,7 +2798,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3927,7 +2834,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10028,7 +10091,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3950,7 +2820,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3950,7 +2856,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10036,7 +10099,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -3973,7 +2842,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3973,7 +2878,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10044,7 +10107,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -3996,7 +2864,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -3996,7 +2900,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10052,7 +10115,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -4019,7 +2886,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4019,7 +2922,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10060,7 +10123,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -4042,7 +2908,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4042,7 +2944,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10068,7 +10131,7 @@ index 0d743c63..6480a01f 100644 }, }, { -@@ -4065,7 +2930,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4065,7 +2966,6 @@ static struct caam_aead_alg driver_aeads .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, .class2_alg_type = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10076,7 +10139,7 @@ index 0d743c63..6480a01f 100644 .geniv = true, }, }, -@@ -4090,7 +2954,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4090,7 +2990,6 @@ static struct caam_aead_alg driver_aeads OP_ALG_AAI_CTR_MOD128, .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10084,7 +10147,7 @@ index 0d743c63..6480a01f 100644 .rfc3686 = true, }, }, -@@ -4115,7 +2978,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4115,7 +3014,6 @@ static struct caam_aead_alg driver_aeads OP_ALG_AAI_CTR_MOD128, .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10092,7 +10155,7 @@ index 0d743c63..6480a01f 100644 .rfc3686 = true, .geniv = true, }, -@@ -4141,7 +3003,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4141,7 +3039,6 @@ static struct caam_aead_alg driver_aeads OP_ALG_AAI_CTR_MOD128, .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10100,7 +10163,7 @@ index 0d743c63..6480a01f 100644 .rfc3686 = true, }, }, -@@ -4166,7 +3027,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4166,7 +3063,6 @@ static struct caam_aead_alg driver_aeads OP_ALG_AAI_CTR_MOD128, .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10108,7 +10171,7 @@ index 0d743c63..6480a01f 100644 .rfc3686 = true, .geniv = true, }, -@@ -4192,7 +3052,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4192,7 +3088,6 @@ static struct caam_aead_alg driver_aeads OP_ALG_AAI_CTR_MOD128, .class2_alg_type = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10116,7 +10179,7 @@ index 0d743c63..6480a01f 100644 .rfc3686 = true, }, }, -@@ -4217,7 +3076,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4217,7 +3112,6 @@ static struct caam_aead_alg driver_aeads OP_ALG_AAI_CTR_MOD128, .class2_alg_type = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10124,7 +10187,7 @@ index 0d743c63..6480a01f 100644 .rfc3686 = true, .geniv = true, }, -@@ -4243,7 +3101,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4243,7 +3137,6 @@ static struct caam_aead_alg driver_aeads OP_ALG_AAI_CTR_MOD128, .class2_alg_type = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10132,7 +10195,7 @@ index 0d743c63..6480a01f 100644 .rfc3686 = true, }, }, -@@ -4268,7 +3125,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4268,7 +3161,6 @@ static struct caam_aead_alg driver_aeads OP_ALG_AAI_CTR_MOD128, .class2_alg_type = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10140,7 +10203,7 @@ index 0d743c63..6480a01f 100644 .rfc3686 = true, .geniv = true, }, -@@ -4294,7 +3150,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4294,7 +3186,6 @@ static struct caam_aead_alg driver_aeads OP_ALG_AAI_CTR_MOD128, .class2_alg_type = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10148,7 +10211,7 @@ index 0d743c63..6480a01f 100644 .rfc3686 = true, }, }, -@@ -4319,7 +3174,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4319,7 +3210,6 @@ static struct caam_aead_alg driver_aeads OP_ALG_AAI_CTR_MOD128, .class2_alg_type = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10156,7 +10219,7 @@ index 0d743c63..6480a01f 100644 .rfc3686 = true, .geniv = true, }, -@@ -4345,7 +3199,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4345,7 +3235,6 @@ static struct caam_aead_alg driver_aeads OP_ALG_AAI_CTR_MOD128, .class2_alg_type = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10164,7 +10227,7 @@ index 0d743c63..6480a01f 100644 .rfc3686 = true, }, }, -@@ -4370,7 +3223,6 @@ static struct caam_aead_alg driver_aeads[] = { +@@ -4370,7 +3259,6 @@ static struct caam_aead_alg driver_aeads OP_ALG_AAI_CTR_MOD128, .class2_alg_type = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC_PRECOMP, @@ -10172,7 +10235,7 @@ index 0d743c63..6480a01f 100644 .rfc3686 = true, .geniv = true, }, -@@ -4385,16 +3237,34 @@ struct caam_crypto_alg { +@@ -4385,16 +3273,34 @@ struct caam_crypto_alg { static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam) { @@ -10210,7 +10273,7 @@ index 0d743c63..6480a01f 100644 return 0; } -@@ -4421,25 +3291,9 @@ static int caam_aead_init(struct crypto_aead *tfm) +@@ -4421,25 +3327,9 @@ static int caam_aead_init(struct crypto_ static void caam_exit_common(struct caam_ctx *ctx) { @@ -10239,7 +10302,7 @@ index 0d743c63..6480a01f 100644 caam_jr_free(ctx->jrdev); } -@@ -4515,7 +3369,6 @@ static struct caam_crypto_alg *caam_alg_alloc(struct caam_alg_template +@@ -4515,7 +3405,6 @@ static struct caam_crypto_alg *caam_alg_ t_alg->caam.class1_alg_type = template->class1_alg_type; t_alg->caam.class2_alg_type = template->class2_alg_type; @@ -10247,12 +10310,9 @@ index 0d743c63..6480a01f 100644 return t_alg; } -diff --git a/drivers/crypto/caam/caamalg_desc.c b/drivers/crypto/caam/caamalg_desc.c -new file mode 100644 -index 00000000..d162120a --- /dev/null +++ b/drivers/crypto/caam/caamalg_desc.c -@@ -0,0 +1,1913 @@ +@@ -0,0 +1,1961 @@ +/* + * Shared descriptors for aead, ablkcipher algorithms + * @@ -10300,16 +10360,16 @@ index 00000000..d162120a + * cnstr_shdsc_aead_null_encap - IPSec ESP encapsulation shared descriptor + * (non-protocol) with no (null) encryption. + * @desc: pointer to buffer used for descriptor construction -+ * @adata: pointer to authentication transform definitions. Note that since a -+ * split key is to be used, the size of the split key itself is -+ * specified. Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, -+ * SHA224, SHA256, SHA384, SHA512} ANDed with OP_ALG_AAI_HMAC_PRECOMP. ++ * @adata: pointer to authentication transform definitions. ++ * A split key is required for SEC Era < 6; the size of the split key ++ * is specified in this case. Valid algorithm values - one of ++ * OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed ++ * with OP_ALG_AAI_HMAC_PRECOMP. + * @icvsize: integrity check value (ICV) size (truncated or full) -+ * -+ * Note: Requires an MDHA split key. ++ * @era: SEC Era + */ +void cnstr_shdsc_aead_null_encap(u32 * const desc, struct alginfo *adata, -+ unsigned int icvsize) ++ unsigned int icvsize, int era) +{ + u32 *key_jump_cmd, *read_move_cmd, *write_move_cmd; + @@ -10318,13 +10378,18 @@ index 00000000..d162120a + /* Skip if already shared */ + key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | + JUMP_COND_SHRD); -+ if (adata->key_inline) -+ append_key_as_imm(desc, adata->key_virt, adata->keylen_pad, -+ adata->keylen, CLASS_2 | KEY_DEST_MDHA_SPLIT | -+ KEY_ENC); -+ else -+ append_key(desc, adata->key_dma, adata->keylen, CLASS_2 | -+ KEY_DEST_MDHA_SPLIT | KEY_ENC); ++ if (era < 6) { ++ if (adata->key_inline) ++ append_key_as_imm(desc, adata->key_virt, ++ adata->keylen_pad, adata->keylen, ++ CLASS_2 | KEY_DEST_MDHA_SPLIT | ++ KEY_ENC); ++ else ++ append_key(desc, adata->key_dma, adata->keylen, ++ CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC); ++ } else { ++ append_proto_dkp(desc, adata); ++ } + set_jump_tgt_here(desc, key_jump_cmd); + + /* assoclen + cryptlen = seqinlen */ @@ -10376,16 +10441,16 @@ index 00000000..d162120a + * cnstr_shdsc_aead_null_decap - IPSec ESP decapsulation shared descriptor + * (non-protocol) with no (null) decryption. + * @desc: pointer to buffer used for descriptor construction -+ * @adata: pointer to authentication transform definitions. Note that since a -+ * split key is to be used, the size of the split key itself is -+ * specified. Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, -+ * SHA224, SHA256, SHA384, SHA512} ANDed with OP_ALG_AAI_HMAC_PRECOMP. ++ * @adata: pointer to authentication transform definitions. ++ * A split key is required for SEC Era < 6; the size of the split key ++ * is specified in this case. Valid algorithm values - one of ++ * OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed ++ * with OP_ALG_AAI_HMAC_PRECOMP. + * @icvsize: integrity check value (ICV) size (truncated or full) -+ * -+ * Note: Requires an MDHA split key. ++ * @era: SEC Era + */ +void cnstr_shdsc_aead_null_decap(u32 * const desc, struct alginfo *adata, -+ unsigned int icvsize) ++ unsigned int icvsize, int era) +{ + u32 *key_jump_cmd, *read_move_cmd, *write_move_cmd, *jump_cmd; + @@ -10394,13 +10459,18 @@ index 00000000..d162120a + /* Skip if already shared */ + key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | + JUMP_COND_SHRD); -+ if (adata->key_inline) -+ append_key_as_imm(desc, adata->key_virt, adata->keylen_pad, -+ adata->keylen, CLASS_2 | -+ KEY_DEST_MDHA_SPLIT | KEY_ENC); -+ else -+ append_key(desc, adata->key_dma, adata->keylen, CLASS_2 | -+ KEY_DEST_MDHA_SPLIT | KEY_ENC); ++ if (era < 6) { ++ if (adata->key_inline) ++ append_key_as_imm(desc, adata->key_virt, ++ adata->keylen_pad, adata->keylen, ++ CLASS_2 | KEY_DEST_MDHA_SPLIT | ++ KEY_ENC); ++ else ++ append_key(desc, adata->key_dma, adata->keylen, ++ CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC); ++ } else { ++ append_proto_dkp(desc, adata); ++ } + set_jump_tgt_here(desc, key_jump_cmd); + + /* Class 2 operation */ @@ -10459,7 +10529,7 @@ index 00000000..d162120a +static void init_sh_desc_key_aead(u32 * const desc, + struct alginfo * const cdata, + struct alginfo * const adata, -+ const bool is_rfc3686, u32 *nonce) ++ const bool is_rfc3686, u32 *nonce, int era) +{ + u32 *key_jump_cmd; + unsigned int enckeylen = cdata->keylen; @@ -10479,13 +10549,18 @@ index 00000000..d162120a + if (is_rfc3686) + enckeylen -= CTR_RFC3686_NONCE_SIZE; + -+ if (adata->key_inline) -+ append_key_as_imm(desc, adata->key_virt, adata->keylen_pad, -+ adata->keylen, CLASS_2 | -+ KEY_DEST_MDHA_SPLIT | KEY_ENC); -+ else -+ append_key(desc, adata->key_dma, adata->keylen, CLASS_2 | -+ KEY_DEST_MDHA_SPLIT | KEY_ENC); ++ if (era < 6) { ++ if (adata->key_inline) ++ append_key_as_imm(desc, adata->key_virt, ++ adata->keylen_pad, adata->keylen, ++ CLASS_2 | KEY_DEST_MDHA_SPLIT | ++ KEY_ENC); ++ else ++ append_key(desc, adata->key_dma, adata->keylen, ++ CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC); ++ } else { ++ append_proto_dkp(desc, adata); ++ } + + if (cdata->key_inline) + append_key_as_imm(desc, cdata->key_virt, enckeylen, @@ -10516,26 +10591,27 @@ index 00000000..d162120a + * @cdata: pointer to block cipher transform definitions + * Valid algorithm values - one of OP_ALG_ALGSEL_{AES, DES, 3DES} ANDed + * with OP_ALG_AAI_CBC or OP_ALG_AAI_CTR_MOD128. -+ * @adata: pointer to authentication transform definitions. Note that since a -+ * split key is to be used, the size of the split key itself is -+ * specified. Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, -+ * SHA224, SHA256, SHA384, SHA512} ANDed with OP_ALG_AAI_HMAC_PRECOMP. ++ * @adata: pointer to authentication transform definitions. ++ * A split key is required for SEC Era < 6; the size of the split key ++ * is specified in this case. Valid algorithm values - one of ++ * OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed ++ * with OP_ALG_AAI_HMAC_PRECOMP. + * @ivsize: initialization vector size + * @icvsize: integrity check value (ICV) size (truncated or full) + * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template + * @nonce: pointer to rfc3686 nonce + * @ctx1_iv_off: IV offset in CONTEXT1 register + * @is_qi: true when called from caam/qi -+ * -+ * Note: Requires an MDHA split key. ++ * @era: SEC Era + */ +void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int ivsize, + unsigned int icvsize, const bool is_rfc3686, -+ u32 *nonce, const u32 ctx1_iv_off, const bool is_qi) ++ u32 *nonce, const u32 ctx1_iv_off, const bool is_qi, ++ int era) +{ + /* Note: Context registers are saved. */ -+ init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce); ++ init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce, era); + + /* Class 2 operation */ + append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL | @@ -10561,8 +10637,13 @@ index 00000000..d162120a + } + + /* Read and write assoclen bytes */ -+ append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ); -+ append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ); ++ if (is_qi || era < 3) { ++ append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ); ++ append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ); ++ } else { ++ append_math_add(desc, VARSEQINLEN, ZERO, DPOVRD, CAAM_CMD_SZ); ++ append_math_add(desc, VARSEQOUTLEN, ZERO, DPOVRD, CAAM_CMD_SZ); ++ } + + /* Skip assoc data */ + append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF); @@ -10605,27 +10686,27 @@ index 00000000..d162120a + * @cdata: pointer to block cipher transform definitions + * Valid algorithm values - one of OP_ALG_ALGSEL_{AES, DES, 3DES} ANDed + * with OP_ALG_AAI_CBC or OP_ALG_AAI_CTR_MOD128. -+ * @adata: pointer to authentication transform definitions. Note that since a -+ * split key is to be used, the size of the split key itself is -+ * specified. Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, -+ * SHA224, SHA256, SHA384, SHA512} ANDed with OP_ALG_AAI_HMAC_PRECOMP. ++ * @adata: pointer to authentication transform definitions. ++ * A split key is required for SEC Era < 6; the size of the split key ++ * is specified in this case. Valid algorithm values - one of ++ * OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed ++ * with OP_ALG_AAI_HMAC_PRECOMP. + * @ivsize: initialization vector size + * @icvsize: integrity check value (ICV) size (truncated or full) + * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template + * @nonce: pointer to rfc3686 nonce + * @ctx1_iv_off: IV offset in CONTEXT1 register + * @is_qi: true when called from caam/qi -+ * -+ * Note: Requires an MDHA split key. ++ * @era: SEC Era + */ +void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int ivsize, + unsigned int icvsize, const bool geniv, + const bool is_rfc3686, u32 *nonce, -+ const u32 ctx1_iv_off, const bool is_qi) ++ const u32 ctx1_iv_off, const bool is_qi, int era) +{ + /* Note: Context registers are saved. */ -+ init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce); ++ init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce, era); + + /* Class 2 operation */ + append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL | @@ -10652,11 +10733,23 @@ index 00000000..d162120a + } + + /* Read and write assoclen bytes */ -+ append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ); -+ if (geniv) -+ append_math_add_imm_u32(desc, VARSEQOUTLEN, REG3, IMM, ivsize); -+ else -+ append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ); ++ if (is_qi || era < 3) { ++ append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ); ++ if (geniv) ++ append_math_add_imm_u32(desc, VARSEQOUTLEN, REG3, IMM, ++ ivsize); ++ else ++ append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, ++ CAAM_CMD_SZ); ++ } else { ++ append_math_add(desc, VARSEQINLEN, ZERO, DPOVRD, CAAM_CMD_SZ); ++ if (geniv) ++ append_math_add_imm_u32(desc, VARSEQOUTLEN, DPOVRD, IMM, ++ ivsize); ++ else ++ append_math_add(desc, VARSEQOUTLEN, ZERO, DPOVRD, ++ CAAM_CMD_SZ); ++ } + + /* Skip assoc data */ + append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF); @@ -10711,29 +10804,29 @@ index 00000000..d162120a + * @cdata: pointer to block cipher transform definitions + * Valid algorithm values - one of OP_ALG_ALGSEL_{AES, DES, 3DES} ANDed + * with OP_ALG_AAI_CBC or OP_ALG_AAI_CTR_MOD128. -+ * @adata: pointer to authentication transform definitions. Note that since a -+ * split key is to be used, the size of the split key itself is -+ * specified. Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, -+ * SHA224, SHA256, SHA384, SHA512} ANDed with OP_ALG_AAI_HMAC_PRECOMP. ++ * @adata: pointer to authentication transform definitions. ++ * A split key is required for SEC Era < 6; the size of the split key ++ * is specified in this case. Valid algorithm values - one of ++ * OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed ++ * with OP_ALG_AAI_HMAC_PRECOMP. + * @ivsize: initialization vector size + * @icvsize: integrity check value (ICV) size (truncated or full) + * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template + * @nonce: pointer to rfc3686 nonce + * @ctx1_iv_off: IV offset in CONTEXT1 register + * @is_qi: true when called from caam/qi -+ * -+ * Note: Requires an MDHA split key. ++ * @era: SEC Era + */ +void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int ivsize, + unsigned int icvsize, const bool is_rfc3686, + u32 *nonce, const u32 ctx1_iv_off, -+ const bool is_qi) ++ const bool is_qi, int era) +{ + u32 geniv, moveiv; + + /* Note: Context registers are saved. */ -+ init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce); ++ init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce, era); + + if (is_qi) { + u32 *wait_load_cmd; @@ -10783,8 +10876,13 @@ index 00000000..d162120a + OP_ALG_ENCRYPT); + + /* Read and write assoclen bytes */ -+ append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ); -+ append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ); ++ if (is_qi || era < 3) { ++ append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ); ++ append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ); ++ } else { ++ append_math_add(desc, VARSEQINLEN, ZERO, DPOVRD, CAAM_CMD_SZ); ++ append_math_add(desc, VARSEQOUTLEN, ZERO, DPOVRD, CAAM_CMD_SZ); ++ } + + /* Skip assoc data */ + append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF); @@ -10843,19 +10941,20 @@ index 00000000..d162120a + * @cdata: pointer to block cipher transform definitions + * Valid algorithm values - one of OP_ALG_ALGSEL_AES ANDed + * with OP_ALG_AAI_CBC -+ * @adata: pointer to authentication transform definitions. Note that since a -+ * split key is to be used, the size of the split key itself is -+ * specified. Valid algorithm values OP_ALG_ALGSEL_SHA1 ANDed with -+ * OP_ALG_AAI_HMAC_PRECOMP. ++ * @adata: pointer to authentication transform definitions. ++ * A split key is required for SEC Era < 6; the size of the split key ++ * is specified in this case. Valid algorithm values OP_ALG_ALGSEL_SHA1 ++ * ANDed with OP_ALG_AAI_HMAC_PRECOMP. + * @assoclen: associated data length + * @ivsize: initialization vector size + * @authsize: authentication data size + * @blocksize: block cipher size ++ * @era: SEC Era + */ +void cnstr_shdsc_tls_encap(u32 * const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int assoclen, + unsigned int ivsize, unsigned int authsize, -+ unsigned int blocksize) ++ unsigned int blocksize, int era) +{ + u32 *key_jump_cmd, *zero_payload_jump_cmd; + u32 genpad, idx_ld_datasz, idx_ld_pad, stidx; @@ -10883,13 +10982,18 @@ index 00000000..d162120a + key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | + JUMP_COND_SHRD); + -+ if (adata->key_inline) -+ append_key_as_imm(desc, adata->key_virt, adata->keylen_pad, -+ adata->keylen, CLASS_2 | KEY_DEST_MDHA_SPLIT | -+ KEY_ENC); -+ else -+ append_key(desc, adata->key_dma, adata->keylen, CLASS_2 | -+ KEY_DEST_MDHA_SPLIT | KEY_ENC); ++ if (era < 6) { ++ if (adata->key_inline) ++ append_key_as_imm(desc, adata->key_virt, ++ adata->keylen_pad, adata->keylen, ++ CLASS_2 | KEY_DEST_MDHA_SPLIT | ++ KEY_ENC); ++ else ++ append_key(desc, adata->key_dma, adata->keylen, ++ CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC); ++ } else { ++ append_proto_dkp(desc, adata); ++ } + + if (cdata->key_inline) + append_key_as_imm(desc, cdata->key_virt, cdata->keylen, @@ -10996,19 +11100,20 @@ index 00000000..d162120a + * @cdata: pointer to block cipher transform definitions + * Valid algorithm values - one of OP_ALG_ALGSEL_AES ANDed + * with OP_ALG_AAI_CBC -+ * @adata: pointer to authentication transform definitions. Note that since a -+ * split key is to be used, the size of the split key itself is -+ * specified. Valid algorithm values OP_ALG_ALGSEL_ SHA1 ANDed with -+ * OP_ALG_AAI_HMAC_PRECOMP. ++ * @adata: pointer to authentication transform definitions. ++ * A split key is required for SEC Era < 6; the size of the split key ++ * is specified in this case. Valid algorithm values OP_ALG_ALGSEL_SHA1 ++ * ANDed with OP_ALG_AAI_HMAC_PRECOMP. + * @assoclen: associated data length + * @ivsize: initialization vector size + * @authsize: authentication data size + * @blocksize: block cipher size ++ * @era: SEC Era + */ +void cnstr_shdsc_tls_decap(u32 * const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int assoclen, + unsigned int ivsize, unsigned int authsize, -+ unsigned int blocksize) ++ unsigned int blocksize, int era) +{ + u32 stidx, jumpback; + u32 *key_jump_cmd, *zero_payload_jump_cmd, *skip_zero_jump_cmd; @@ -11026,8 +11131,11 @@ index 00000000..d162120a + key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | + JUMP_COND_SHRD); + -+ append_key(desc, adata->key_dma, adata->keylen, CLASS_2 | -+ KEY_DEST_MDHA_SPLIT | KEY_ENC); ++ if (era < 6) ++ append_key(desc, adata->key_dma, adata->keylen, CLASS_2 | ++ KEY_DEST_MDHA_SPLIT | KEY_ENC); ++ else ++ append_proto_dkp(desc, adata); + + append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 | + KEY_DEST_CLASS_REG); @@ -11873,7 +11981,7 @@ index 00000000..d162120a + + /* Load nonce into CONTEXT1 reg */ + if (is_rfc3686) { -+ u8 *nonce = cdata->key_virt + cdata->keylen; ++ const u8 *nonce = cdata->key_virt + cdata->keylen; + + append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE, + LDST_CLASS_IND_CCB | @@ -11938,7 +12046,7 @@ index 00000000..d162120a + + /* Load nonce into CONTEXT1 reg */ + if (is_rfc3686) { -+ u8 *nonce = cdata->key_virt + cdata->keylen; ++ const u8 *nonce = cdata->key_virt + cdata->keylen; + + append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE, + LDST_CLASS_IND_CCB | @@ -12007,7 +12115,7 @@ index 00000000..d162120a + + /* Load Nonce into CONTEXT1 reg */ + if (is_rfc3686) { -+ u8 *nonce = cdata->key_virt + cdata->keylen; ++ const u8 *nonce = cdata->key_virt + cdata->keylen; + + append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE, + LDST_CLASS_IND_CCB | @@ -12166,9 +12274,6 @@ index 00000000..d162120a +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("FSL CAAM descriptor support"); +MODULE_AUTHOR("Freescale Semiconductor - NMG/STC"); -diff --git a/drivers/crypto/caam/caamalg_desc.h b/drivers/crypto/caam/caamalg_desc.h -new file mode 100644 -index 00000000..6b436f65 --- /dev/null +++ b/drivers/crypto/caam/caamalg_desc.h @@ -0,0 +1,127 @@ @@ -12225,38 +12330,38 @@ index 00000000..6b436f65 + 15 * CAAM_CMD_SZ) + +void cnstr_shdsc_aead_null_encap(u32 * const desc, struct alginfo *adata, -+ unsigned int icvsize); ++ unsigned int icvsize, int era); + +void cnstr_shdsc_aead_null_decap(u32 * const desc, struct alginfo *adata, -+ unsigned int icvsize); ++ unsigned int icvsize, int era); + +void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int ivsize, + unsigned int icvsize, const bool is_rfc3686, + u32 *nonce, const u32 ctx1_iv_off, -+ const bool is_qi); ++ const bool is_qi, int era); + +void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int ivsize, + unsigned int icvsize, const bool geniv, + const bool is_rfc3686, u32 *nonce, -+ const u32 ctx1_iv_off, const bool is_qi); ++ const u32 ctx1_iv_off, const bool is_qi, int era); + +void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int ivsize, + unsigned int icvsize, const bool is_rfc3686, + u32 *nonce, const u32 ctx1_iv_off, -+ const bool is_qi); ++ const bool is_qi, int era); + +void cnstr_shdsc_tls_encap(u32 *const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int assoclen, + unsigned int ivsize, unsigned int authsize, -+ unsigned int blocksize); ++ unsigned int blocksize, int era); + +void cnstr_shdsc_tls_decap(u32 *const desc, struct alginfo *cdata, + struct alginfo *adata, unsigned int assoclen, + unsigned int ivsize, unsigned int authsize, -+ unsigned int blocksize); ++ unsigned int blocksize, int era); + +void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata, + unsigned int ivsize, unsigned int icvsize, @@ -12299,12 +12404,9 @@ index 00000000..6b436f65 +void cnstr_shdsc_xts_ablkcipher_decap(u32 * const desc, struct alginfo *cdata); + +#endif /* _CAAMALG_DESC_H_ */ -diff --git a/drivers/crypto/caam/caamalg_qi.c b/drivers/crypto/caam/caamalg_qi.c -new file mode 100644 -index 00000000..d6a9b0c5 --- /dev/null +++ b/drivers/crypto/caam/caamalg_qi.c -@@ -0,0 +1,2877 @@ +@@ -0,0 +1,2929 @@ +/* + * Freescale FSL CAAM support for crypto API over QI backend. + * Based on caamalg.c @@ -12381,6 +12483,7 @@ index 00000000..d6a9b0c5 + const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) == + OP_ALG_AAI_CTR_MOD128); + const bool is_rfc3686 = alg->caam.rfc3686; ++ struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent); + + if (!ctx->cdata.keylen || !ctx->authsize) + return 0; @@ -12431,7 +12534,7 @@ index 00000000..d6a9b0c5 + + cnstr_shdsc_aead_encap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata, + ivsize, ctx->authsize, is_rfc3686, nonce, -+ ctx1_iv_off, true); ++ ctx1_iv_off, true, ctrlpriv->era); + +skip_enc: + /* aead_decrypt shared descriptor */ @@ -12456,7 +12559,8 @@ index 00000000..d6a9b0c5 + + cnstr_shdsc_aead_decap(ctx->sh_desc_dec, &ctx->cdata, &ctx->adata, + ivsize, ctx->authsize, alg->caam.geniv, -+ is_rfc3686, nonce, ctx1_iv_off, true); ++ is_rfc3686, nonce, ctx1_iv_off, true, ++ ctrlpriv->era); + + if (!alg->caam.geniv) + goto skip_givenc; @@ -12483,7 +12587,7 @@ index 00000000..d6a9b0c5 + + cnstr_shdsc_aead_givencap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata, + ivsize, ctx->authsize, is_rfc3686, nonce, -+ ctx1_iv_off, true); ++ ctx1_iv_off, true, ctrlpriv->era); + +skip_givenc: + return 0; @@ -12504,6 +12608,7 @@ index 00000000..d6a9b0c5 +{ + struct caam_ctx *ctx = crypto_aead_ctx(aead); + struct device *jrdev = ctx->jrdev; ++ struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent); + struct crypto_authenc_keys keys; + int ret = 0; + @@ -12518,6 +12623,27 @@ index 00000000..d6a9b0c5 + DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); +#endif + ++ /* ++ * If DKP is supported, use it in the shared descriptor to generate ++ * the split key. ++ */ ++ if (ctrlpriv->era >= 6) { ++ ctx->adata.keylen = keys.authkeylen; ++ ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & ++ OP_ALG_ALGSEL_MASK); ++ ++ if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE) ++ goto badkey; ++ ++ memcpy(ctx->key, keys.authkey, keys.authkeylen); ++ memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, ++ keys.enckeylen); ++ dma_sync_single_for_device(jrdev, ctx->key_dma, ++ ctx->adata.keylen_pad + ++ keys.enckeylen, DMA_TO_DEVICE); ++ goto skip_split_key; ++ } ++ + ret = gen_split_key(jrdev, ctx->key, &ctx->adata, keys.authkey, + keys.authkeylen, CAAM_MAX_KEY_SIZE - + keys.enckeylen); @@ -12534,6 +12660,7 @@ index 00000000..d6a9b0c5 + ctx->adata.keylen_pad + keys.enckeylen, 1); +#endif + ++skip_split_key: + ctx->cdata.keylen = keys.enckeylen; + + ret = aead_set_sh_desc(aead); @@ -12573,6 +12700,7 @@ index 00000000..d6a9b0c5 + unsigned int assoclen = 13; /* always 13 bytes for TLS */ + unsigned int data_len[2]; + u32 inl_mask; ++ struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent); + + if (!ctx->cdata.keylen || !ctx->authsize) + return 0; @@ -12603,17 +12731,20 @@ index 00000000..d6a9b0c5 + ctx->cdata.key_inline = !!(inl_mask & 2); + + cnstr_shdsc_tls_encap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata, -+ assoclen, ivsize, ctx->authsize, blocksize); ++ assoclen, ivsize, ctx->authsize, blocksize, ++ ctrlpriv->era); + + /* + * TLS 1.0 decrypt shared descriptor + * Keys do not fit inline, regardless of algorithms used + */ ++ ctx->adata.key_inline = false; + ctx->adata.key_dma = ctx->key_dma; + ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; + + cnstr_shdsc_tls_decap(ctx->sh_desc_dec, &ctx->cdata, &ctx->adata, -+ assoclen, ivsize, ctx->authsize, blocksize); ++ assoclen, ivsize, ctx->authsize, blocksize, ++ ctrlpriv->era); + + return 0; +} @@ -12633,6 +12764,7 @@ index 00000000..d6a9b0c5 +{ + struct caam_ctx *ctx = crypto_aead_ctx(tls); + struct device *jrdev = ctx->jrdev; ++ struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent); + struct crypto_authenc_keys keys; + int ret = 0; + @@ -12647,10 +12779,31 @@ index 00000000..d6a9b0c5 + DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); +#endif + -+ ret = gen_split_key(jrdev, ctx->key, &ctx->adata, keys.authkey, -+ keys.authkeylen, CAAM_MAX_KEY_SIZE - -+ keys.enckeylen); -+ if (ret) ++ /* ++ * If DKP is supported, use it in the shared descriptor to generate ++ * the split key. ++ */ ++ if (ctrlpriv->era >= 6) { ++ ctx->adata.keylen = keys.authkeylen; ++ ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & ++ OP_ALG_ALGSEL_MASK); ++ ++ if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE) ++ goto badkey; ++ ++ memcpy(ctx->key, keys.authkey, keys.authkeylen); ++ memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, ++ keys.enckeylen); ++ dma_sync_single_for_device(jrdev, ctx->key_dma, ++ ctx->adata.keylen_pad + ++ keys.enckeylen, DMA_TO_DEVICE); ++ goto skip_split_key; ++ } ++ ++ ret = gen_split_key(jrdev, ctx->key, &ctx->adata, keys.authkey, ++ keys.authkeylen, CAAM_MAX_KEY_SIZE - ++ keys.enckeylen); ++ if (ret) + goto badkey; + + /* postpend encryption key to auth split key */ @@ -12666,6 +12819,7 @@ index 00000000..d6a9b0c5 + ctx->adata.keylen_pad + keys.enckeylen, 1); +#endif + ++skip_split_key: + ctx->cdata.keylen = keys.enckeylen; + + ret = tls_set_sh_desc(tls); @@ -15182,12 +15336,9 @@ index 00000000..d6a9b0c5 +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Support for crypto API using CAAM-QI backend"); +MODULE_AUTHOR("Freescale Semiconductor"); -diff --git a/drivers/crypto/caam/caamalg_qi2.c b/drivers/crypto/caam/caamalg_qi2.c -new file mode 100644 -index 00000000..102b0841 --- /dev/null +++ b/drivers/crypto/caam/caamalg_qi2.c -@@ -0,0 +1,4428 @@ +@@ -0,0 +1,5920 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor Inc. + * Copyright 2017 NXP @@ -15232,6 +15383,7 @@ index 00000000..102b0841 +#include "sg_sw_qm2.h" +#include "key_gen.h" +#include "caamalg_desc.h" ++#include "caamhash_desc.h" +#include "../../../drivers/staging/fsl-mc/include/mc.h" +#include "../../../drivers/staging/fsl-mc/include/dpaa2-io.h" +#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h" @@ -15278,6 +15430,7 @@ index 00000000..102b0841 + * caam_ctx - per-session context + * @flc: Flow Contexts array + * @key: virtual address of the key(s): [authentication key], encryption key ++ * @flc_dma: I/O virtual addresses of the Flow Contexts + * @key_dma: I/O virtual address of the key + * @dev: dpseci device + * @adata: authentication algorithm details @@ -15287,6 +15440,7 @@ index 00000000..102b0841 +struct caam_ctx { + struct caam_flc flc[NUM_OP]; + u8 key[CAAM_MAX_KEY_SIZE]; ++ dma_addr_t flc_dma[NUM_OP]; + dma_addr_t key_dma; + struct device *dev; + struct alginfo adata; @@ -15344,6 +15498,8 @@ index 00000000..102b0841 + case CRYPTO_ALG_TYPE_AEAD: + return aead_request_ctx(container_of(areq, struct aead_request, + base)); ++ case CRYPTO_ALG_TYPE_AHASH: ++ return ahash_request_ctx(ahash_request_cast(areq)); + default: + return ERR_PTR(-EINVAL); + } @@ -15379,6 +15535,7 @@ index 00000000..102b0841 + struct caam_ctx *ctx = crypto_aead_ctx(aead); + unsigned int ivsize = crypto_aead_ivsize(aead); + struct device *dev = ctx->dev; ++ struct dpaa2_caam_priv *priv = dev_get_drvdata(dev); + struct caam_flc *flc; + u32 *desc; + u32 ctx1_iv_off = 0; @@ -15440,19 +15597,17 @@ index 00000000..102b0841 + if (alg->caam.geniv) + cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata, + ivsize, ctx->authsize, is_rfc3686, -+ nonce, ctx1_iv_off, true); ++ nonce, ctx1_iv_off, true, ++ priv->sec_attr.era); + else + cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, + ivsize, ctx->authsize, is_rfc3686, nonce, -+ ctx1_iv_off, true); ++ ctx1_iv_off, true, priv->sec_attr.era); + + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + /* aead_decrypt shared descriptor */ + if (desc_inline_query(DESC_QI_AEAD_DEC_LEN + @@ -15476,18 +15631,14 @@ index 00000000..102b0841 + + flc = &ctx->flc[DECRYPT]; + desc = flc->sh_desc; -+ + cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata, + ivsize, ctx->authsize, alg->caam.geniv, -+ is_rfc3686, nonce, ctx1_iv_off, true); -+ ++ is_rfc3686, nonce, ctx1_iv_off, true, ++ priv->sec_attr.era); + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + return 0; +} @@ -15523,137 +15674,12 @@ index 00000000..102b0841 + complete(&res->completion); +} + -+static int gen_split_key_sh(struct device *dev, u8 *key_out, -+ struct alginfo * const adata, const u8 *key_in, -+ u32 keylen) -+{ -+ struct caam_request *req_ctx; -+ u32 *desc; -+ struct split_key_sh_result result; -+ dma_addr_t dma_addr_in, dma_addr_out; -+ struct caam_flc *flc; -+ struct dpaa2_fl_entry *in_fle, *out_fle; -+ int ret = -ENOMEM; -+ -+ req_ctx = kzalloc(sizeof(*req_ctx), GFP_KERNEL | GFP_DMA); -+ if (!req_ctx) -+ return -ENOMEM; -+ -+ in_fle = &req_ctx->fd_flt[1]; -+ out_fle = &req_ctx->fd_flt[0]; -+ -+ flc = kzalloc(sizeof(*flc), GFP_KERNEL | GFP_DMA); -+ if (!flc) -+ goto err_flc; -+ -+ dma_addr_in = dma_map_single(dev, (void *)key_in, keylen, -+ DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, dma_addr_in)) { -+ dev_err(dev, "unable to map key input memory\n"); -+ goto err_dma_addr_in; -+ } -+ -+ dma_addr_out = dma_map_single(dev, key_out, adata->keylen_pad, -+ DMA_FROM_DEVICE); -+ if (dma_mapping_error(dev, dma_addr_out)) { -+ dev_err(dev, "unable to map key output memory\n"); -+ goto err_dma_addr_out; -+ } -+ -+ desc = flc->sh_desc; -+ -+ init_sh_desc(desc, 0); -+ append_key(desc, dma_addr_in, keylen, CLASS_2 | KEY_DEST_CLASS_REG); -+ -+ /* Sets MDHA up into an HMAC-INIT */ -+ append_operation(desc, (adata->algtype & OP_ALG_ALGSEL_MASK) | -+ OP_ALG_AAI_HMAC | OP_TYPE_CLASS2_ALG | OP_ALG_DECRYPT | -+ OP_ALG_AS_INIT); -+ -+ /* -+ * do a FIFO_LOAD of zero, this will trigger the internal key expansion -+ * into both pads inside MDHA -+ */ -+ append_fifo_load_as_imm(desc, NULL, 0, LDST_CLASS_2_CCB | -+ FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST2); -+ -+ /* -+ * FIFO_STORE with the explicit split-key content store -+ * (0x26 output type) -+ */ -+ append_fifo_store(desc, dma_addr_out, adata->keylen, -+ LDST_CLASS_2_CCB | FIFOST_TYPE_SPLIT_KEK); -+ -+ flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ goto err_flc_dma; -+ } -+ -+ dpaa2_fl_set_final(in_fle, true); -+ dpaa2_fl_set_format(in_fle, dpaa2_fl_single); -+ dpaa2_fl_set_addr(in_fle, dma_addr_in); -+ dpaa2_fl_set_len(in_fle, keylen); -+ dpaa2_fl_set_format(out_fle, dpaa2_fl_single); -+ dpaa2_fl_set_addr(out_fle, dma_addr_out); -+ dpaa2_fl_set_len(out_fle, adata->keylen_pad); -+ -+#ifdef DEBUG -+ print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, key_in, keylen, 1); -+ print_hex_dump(KERN_ERR, "desc@" __stringify(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); -+#endif -+ -+ result.err = 0; -+ init_completion(&result.completion); -+ result.dev = dev; -+ -+ req_ctx->flc = flc; -+ req_ctx->cbk = split_key_sh_done; -+ req_ctx->ctx = &result; -+ -+ ret = dpaa2_caam_enqueue(dev, req_ctx); -+ if (ret == -EINPROGRESS) { -+ /* in progress */ -+ wait_for_completion(&result.completion); -+ ret = result.err; -+#ifdef DEBUG -+ print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, key_out, -+ adata->keylen_pad, 1); -+#endif -+ } -+ -+ dma_unmap_single(dev, flc->flc_dma, sizeof(flc->flc) + desc_bytes(desc), -+ DMA_TO_DEVICE); -+err_flc_dma: -+ dma_unmap_single(dev, dma_addr_out, adata->keylen_pad, DMA_FROM_DEVICE); -+err_dma_addr_out: -+ dma_unmap_single(dev, dma_addr_in, keylen, DMA_TO_DEVICE); -+err_dma_addr_in: -+ kfree(flc); -+err_flc: -+ kfree(req_ctx); -+ return ret; -+} -+ -+static int gen_split_aead_key(struct caam_ctx *ctx, const u8 *key_in, -+ u32 authkeylen) -+{ -+ return gen_split_key_sh(ctx->dev, ctx->key, &ctx->adata, key_in, -+ authkeylen); -+} -+ +static int aead_setkey(struct crypto_aead *aead, const u8 *key, + unsigned int keylen) +{ + struct caam_ctx *ctx = crypto_aead_ctx(aead); + struct device *dev = ctx->dev; + struct crypto_authenc_keys keys; -+ int ret; + + if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) + goto badkey; @@ -15666,34 +15692,17 @@ index 00000000..102b0841 + DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); +#endif + -+ ctx->adata.keylen = split_key_len(ctx->adata.algtype & -+ OP_ALG_ALGSEL_MASK); -+ ctx->adata.keylen_pad = split_key_pad_len(ctx->adata.algtype & -+ OP_ALG_ALGSEL_MASK); -+ -+#ifdef DEBUG -+ dev_err(dev, "split keylen %d split keylen padded %d\n", -+ ctx->adata.keylen, ctx->adata.keylen_pad); -+ print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, keys.authkey, keylen, 1); -+#endif ++ ctx->adata.keylen = keys.authkeylen; ++ ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & ++ OP_ALG_ALGSEL_MASK); + + if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE) + goto badkey; + -+ ret = gen_split_aead_key(ctx, keys.authkey, keys.authkeylen); -+ if (ret) -+ goto badkey; -+ -+ /* postpend encryption key to auth split key */ ++ memcpy(ctx->key, keys.authkey, keys.authkeylen); + memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen); -+ -+ ctx->key_dma = dma_map_single(dev, ctx->key, ctx->adata.keylen_pad + -+ keys.enckeylen, DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, ctx->key_dma)) { -+ dev_err(dev, "unable to map key i/o memory\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->key_dma, ctx->adata.keylen_pad + ++ keys.enckeylen, DMA_BIDIRECTIONAL); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, @@ -15702,12 +15711,7 @@ index 00000000..102b0841 + + ctx->cdata.keylen = keys.enckeylen; + -+ ret = aead_set_sh_desc(aead); -+ if (ret) -+ dma_unmap_single(dev, ctx->key_dma, ctx->adata.keylen_pad + -+ keys.enckeylen, DMA_TO_DEVICE); -+ -+ return ret; ++ return aead_set_sh_desc(aead); +badkey: + crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN); + return -EINVAL; @@ -16091,6 +16095,7 @@ index 00000000..102b0841 + unsigned int ivsize = crypto_aead_ivsize(tls); + unsigned int blocksize = crypto_aead_blocksize(tls); + struct device *dev = ctx->dev; ++ struct dpaa2_caam_priv *priv = dev_get_drvdata(dev); + struct caam_flc *flc; + u32 *desc; + unsigned int assoclen = 13; /* always 13 bytes for TLS */ @@ -16127,39 +16132,30 @@ index 00000000..102b0841 + + flc = &ctx->flc[ENCRYPT]; + desc = flc->sh_desc; -+ + cnstr_shdsc_tls_encap(desc, &ctx->cdata, &ctx->adata, -+ assoclen, ivsize, ctx->authsize, blocksize); -+ ++ assoclen, ivsize, ctx->authsize, blocksize, ++ priv->sec_attr.era); + flc->flc[1] = desc_len(desc); -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + /* + * TLS 1.0 decrypt shared descriptor + * Keys do not fit inline, regardless of algorithms used + */ ++ ctx->adata.key_inline = false; + ctx->adata.key_dma = ctx->key_dma; + ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad; + + flc = &ctx->flc[DECRYPT]; + desc = flc->sh_desc; -+ + cnstr_shdsc_tls_decap(desc, &ctx->cdata, &ctx->adata, assoclen, ivsize, -+ ctx->authsize, blocksize); -+ ++ ctx->authsize, blocksize, priv->sec_attr.era); + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + return 0; +} @@ -16170,7 +16166,6 @@ index 00000000..102b0841 + struct caam_ctx *ctx = crypto_aead_ctx(tls); + struct device *dev = ctx->dev; + struct crypto_authenc_keys keys; -+ int ret; + + if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) + goto badkey; @@ -16183,35 +16178,17 @@ index 00000000..102b0841 + DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); +#endif + -+ ctx->adata.keylen = split_key_len(ctx->adata.algtype & -+ OP_ALG_ALGSEL_MASK); -+ ctx->adata.keylen_pad = split_key_pad_len(ctx->adata.algtype & -+ OP_ALG_ALGSEL_MASK); -+ -+#ifdef DEBUG -+ dev_err(dev, "split keylen %d split keylen padded %d\n", -+ ctx->adata.keylen, ctx->adata.keylen_pad); -+ print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, keys.authkey, -+ keys.authkeylen + keys.enckeylen, 1); -+#endif ++ ctx->adata.keylen = keys.authkeylen; ++ ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & ++ OP_ALG_ALGSEL_MASK); + + if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE) + goto badkey; + -+ ret = gen_split_aead_key(ctx, keys.authkey, keys.authkeylen); -+ if (ret) -+ goto badkey; -+ -+ /* postpend encryption key to auth split key */ ++ memcpy(ctx->key, keys.authkey, keys.authkeylen); + memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen); -+ -+ ctx->key_dma = dma_map_single(dev, ctx->key, ctx->adata.keylen_pad + -+ keys.enckeylen, DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, ctx->key_dma)) { -+ dev_err(dev, "unable to map key i/o memory\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->key_dma, ctx->adata.keylen_pad + ++ keys.enckeylen, DMA_BIDIRECTIONAL); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, @@ -16220,12 +16197,7 @@ index 00000000..102b0841 + + ctx->cdata.keylen = keys.enckeylen; + -+ ret = tls_set_sh_desc(tls); -+ if (ret) -+ dma_unmap_single(dev, ctx->key_dma, ctx->adata.keylen_pad + -+ keys.enckeylen, DMA_TO_DEVICE); -+ -+ return ret; ++ return tls_set_sh_desc(tls); +badkey: + crypto_aead_set_flags(tls, CRYPTO_TFM_RES_BAD_KEY_LEN); + return -EINVAL; @@ -16270,14 +16242,10 @@ index 00000000..102b0841 + flc = &ctx->flc[ENCRYPT]; + desc = flc->sh_desc; + cnstr_shdsc_gcm_encap(desc, &ctx->cdata, ivsize, ctx->authsize, true); -+ + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + /* + * Job Descriptor and Shared Descriptors @@ -16294,14 +16262,10 @@ index 00000000..102b0841 + flc = &ctx->flc[DECRYPT]; + desc = flc->sh_desc; + cnstr_shdsc_gcm_decap(desc, &ctx->cdata, ivsize, ctx->authsize, true); -+ + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + return 0; +} @@ -16321,7 +16285,6 @@ index 00000000..102b0841 +{ + struct caam_ctx *ctx = crypto_aead_ctx(aead); + struct device *dev = ctx->dev; -+ int ret; + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ", @@ -16329,19 +16292,11 @@ index 00000000..102b0841 +#endif + + memcpy(ctx->key, key, keylen); -+ ctx->key_dma = dma_map_single(dev, ctx->key, keylen, DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, ctx->key_dma)) { -+ dev_err(dev, "unable to map key i/o memory\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->key_dma, keylen, ++ DMA_BIDIRECTIONAL); + ctx->cdata.keylen = keylen; + -+ ret = gcm_set_sh_desc(aead); -+ if (ret) -+ dma_unmap_single(dev, ctx->key_dma, ctx->cdata.keylen, -+ DMA_TO_DEVICE); -+ -+ return ret; ++ return gcm_set_sh_desc(aead); +} + +static int rfc4106_set_sh_desc(struct crypto_aead *aead) @@ -16375,14 +16330,10 @@ index 00000000..102b0841 + desc = flc->sh_desc; + cnstr_shdsc_rfc4106_encap(desc, &ctx->cdata, ivsize, ctx->authsize, + true); -+ + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + /* + * Job Descriptor and Shared Descriptors @@ -16399,14 +16350,10 @@ index 00000000..102b0841 + desc = flc->sh_desc; + cnstr_shdsc_rfc4106_decap(desc, &ctx->cdata, ivsize, ctx->authsize, + true); -+ + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + return 0; +} @@ -16427,7 +16374,6 @@ index 00000000..102b0841 +{ + struct caam_ctx *ctx = crypto_aead_ctx(aead); + struct device *dev = ctx->dev; -+ int ret; + + if (keylen < 4) + return -EINVAL; @@ -16443,19 +16389,10 @@ index 00000000..102b0841 + * in the nonce. Update the AES key length. + */ + ctx->cdata.keylen = keylen - 4; -+ ctx->key_dma = dma_map_single(dev, ctx->key, ctx->cdata.keylen, -+ DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, ctx->key_dma)) { -+ dev_err(dev, "unable to map key i/o memory\n"); -+ return -ENOMEM; -+ } -+ -+ ret = rfc4106_set_sh_desc(aead); -+ if (ret) -+ dma_unmap_single(dev, ctx->key_dma, ctx->cdata.keylen, -+ DMA_TO_DEVICE); ++ dma_sync_single_for_device(dev, ctx->key_dma, ctx->cdata.keylen, ++ DMA_BIDIRECTIONAL); + -+ return ret; ++ return rfc4106_set_sh_desc(aead); +} + +static int rfc4543_set_sh_desc(struct crypto_aead *aead) @@ -16489,14 +16426,10 @@ index 00000000..102b0841 + desc = flc->sh_desc; + cnstr_shdsc_rfc4543_encap(desc, &ctx->cdata, ivsize, ctx->authsize, + true); -+ + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + /* + * Job Descriptor and Shared Descriptors @@ -16513,14 +16446,10 @@ index 00000000..102b0841 + desc = flc->sh_desc; + cnstr_shdsc_rfc4543_decap(desc, &ctx->cdata, ivsize, ctx->authsize, + true); -+ + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + return 0; +} @@ -16541,7 +16470,6 @@ index 00000000..102b0841 +{ + struct caam_ctx *ctx = crypto_aead_ctx(aead); + struct device *dev = ctx->dev; -+ int ret; + + if (keylen < 4) + return -EINVAL; @@ -16557,19 +16485,10 @@ index 00000000..102b0841 + * in the nonce. Update the AES key length. + */ + ctx->cdata.keylen = keylen - 4; -+ ctx->key_dma = dma_map_single(dev, ctx->key, ctx->cdata.keylen, -+ DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, ctx->key_dma)) { -+ dev_err(dev, "unable to map key i/o memory\n"); -+ return -ENOMEM; -+ } -+ -+ ret = rfc4543_set_sh_desc(aead); -+ if (ret) -+ dma_unmap_single(dev, ctx->key_dma, ctx->cdata.keylen, -+ DMA_TO_DEVICE); ++ dma_sync_single_for_device(dev, ctx->key_dma, ctx->cdata.keylen, ++ DMA_BIDIRECTIONAL); + -+ return ret; ++ return rfc4543_set_sh_desc(aead); +} + +static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher, @@ -16587,7 +16506,6 @@ index 00000000..102b0841 + OP_ALG_AAI_CTR_MOD128); + const bool is_rfc3686 = (ctr_mode && strstr(alg_name, "rfc3686")); + -+ memcpy(ctx->key, key, keylen); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); @@ -16610,59 +16528,39 @@ index 00000000..102b0841 + keylen -= CTR_RFC3686_NONCE_SIZE; + } + -+ ctx->key_dma = dma_map_single(dev, ctx->key, keylen, DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, ctx->key_dma)) { -+ dev_err(dev, "unable to map key i/o memory\n"); -+ return -ENOMEM; -+ } + ctx->cdata.keylen = keylen; -+ ctx->cdata.key_virt = ctx->key; ++ ctx->cdata.key_virt = key; + ctx->cdata.key_inline = true; + + /* ablkcipher_encrypt shared descriptor */ + flc = &ctx->flc[ENCRYPT]; + desc = flc->sh_desc; -+ + cnstr_shdsc_ablkcipher_encap(desc, &ctx->cdata, ivsize, + is_rfc3686, ctx1_iv_off); -+ + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + /* ablkcipher_decrypt shared descriptor */ + flc = &ctx->flc[DECRYPT]; + desc = flc->sh_desc; -+ + cnstr_shdsc_ablkcipher_decap(desc, &ctx->cdata, ivsize, + is_rfc3686, ctx1_iv_off); -+ + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + /* ablkcipher_givencrypt shared descriptor */ + flc = &ctx->flc[GIVENCRYPT]; + desc = flc->sh_desc; -+ + cnstr_shdsc_ablkcipher_givencap(desc, &ctx->cdata, + ivsize, is_rfc3686, ctx1_iv_off); -+ + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[GIVENCRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + return 0; +} @@ -16682,42 +16580,27 @@ index 00000000..102b0841 + return -EINVAL; + } + -+ memcpy(ctx->key, key, keylen); -+ ctx->key_dma = dma_map_single(dev, ctx->key, keylen, DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, ctx->key_dma)) { -+ dev_err(dev, "unable to map key i/o memory\n"); -+ return -ENOMEM; -+ } + ctx->cdata.keylen = keylen; -+ ctx->cdata.key_virt = ctx->key; ++ ctx->cdata.key_virt = key; + ctx->cdata.key_inline = true; + + /* xts_ablkcipher_encrypt shared descriptor */ + flc = &ctx->flc[ENCRYPT]; + desc = flc->sh_desc; + cnstr_shdsc_xts_ablkcipher_encap(desc, &ctx->cdata); -+ + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + /* xts_ablkcipher_decrypt shared descriptor */ + flc = &ctx->flc[DECRYPT]; + desc = flc->sh_desc; -+ + cnstr_shdsc_xts_ablkcipher_decap(desc, &ctx->cdata); -+ + flc->flc[1] = desc_len(desc); /* SDL */ -+ flc->flc_dma = dma_map_single(dev, flc, sizeof(flc->flc) + -+ desc_bytes(desc), DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, flc->flc_dma)) { -+ dev_err(dev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } ++ dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT], ++ sizeof(flc->flc) + desc_bytes(desc), ++ DMA_BIDIRECTIONAL); + + return 0; +} @@ -17130,6 +17013,7 @@ index 00000000..102b0841 + return PTR_ERR(edesc); + + caam_req->flc = &ctx->flc[ENCRYPT]; ++ caam_req->flc_dma = ctx->flc_dma[ENCRYPT]; + caam_req->op_type = ENCRYPT; + caam_req->cbk = aead_encrypt_done; + caam_req->ctx = &req->base; @@ -17158,6 +17042,7 @@ index 00000000..102b0841 + return PTR_ERR(edesc); + + caam_req->flc = &ctx->flc[DECRYPT]; ++ caam_req->flc_dma = ctx->flc_dma[DECRYPT]; + caam_req->op_type = DECRYPT; + caam_req->cbk = aead_decrypt_done; + caam_req->ctx = &req->base; @@ -17243,6 +17128,7 @@ index 00000000..102b0841 + return PTR_ERR(edesc); + + caam_req->flc = &ctx->flc[ENCRYPT]; ++ caam_req->flc_dma = ctx->flc_dma[ENCRYPT]; + caam_req->op_type = ENCRYPT; + caam_req->cbk = tls_encrypt_done; + caam_req->ctx = &req->base; @@ -17271,6 +17157,7 @@ index 00000000..102b0841 + return PTR_ERR(edesc); + + caam_req->flc = &ctx->flc[DECRYPT]; ++ caam_req->flc_dma = ctx->flc_dma[DECRYPT]; + caam_req->op_type = DECRYPT; + caam_req->cbk = tls_decrypt_done; + caam_req->ctx = &req->base; @@ -17357,6 +17244,7 @@ index 00000000..102b0841 + return PTR_ERR(edesc); + + caam_req->flc = &ctx->flc[ENCRYPT]; ++ caam_req->flc_dma = ctx->flc_dma[ENCRYPT]; + caam_req->op_type = ENCRYPT; + caam_req->cbk = ablkcipher_done; + caam_req->ctx = &req->base; @@ -17386,6 +17274,7 @@ index 00000000..102b0841 + return PTR_ERR(edesc); + + caam_req->flc = &ctx->flc[GIVENCRYPT]; ++ caam_req->flc_dma = ctx->flc_dma[GIVENCRYPT]; + caam_req->op_type = GIVENCRYPT; + caam_req->cbk = ablkcipher_done; + caam_req->ctx = &req->base; @@ -17414,6 +17303,7 @@ index 00000000..102b0841 + return PTR_ERR(edesc); + + caam_req->flc = &ctx->flc[DECRYPT]; ++ caam_req->flc_dma = ctx->flc_dma[DECRYPT]; + caam_req->op_type = DECRYPT; + caam_req->cbk = ablkcipher_done; + caam_req->ctx = &req->base; @@ -17440,6 +17330,8 @@ index 00000000..102b0841 + struct caam_crypto_alg *caam_alg = container_of(alg, typeof(*caam_alg), + crypto_alg); + struct caam_ctx *ctx = crypto_tfm_ctx(tfm); ++ dma_addr_t dma_addr; ++ int i; + + /* copy descriptor header template value */ + ctx->cdata.algtype = OP_TYPE_CLASS1_ALG | @@ -17449,6 +17341,19 @@ index 00000000..102b0841 + + ctx->dev = caam_alg->caam.dev; + ++ dma_addr = dma_map_single_attrs(ctx->dev, ctx->flc, ++ offsetof(struct caam_ctx, flc_dma), ++ DMA_BIDIRECTIONAL, ++ DMA_ATTR_SKIP_CPU_SYNC); ++ if (dma_mapping_error(ctx->dev, dma_addr)) { ++ dev_err(ctx->dev, "unable to map key, shared descriptors\n"); ++ return -ENOMEM; ++ } ++ ++ for (i = 0; i < NUM_OP; i++) ++ ctx->flc_dma[i] = dma_addr + i * sizeof(ctx->flc[i]); ++ ctx->key_dma = dma_addr + NUM_OP * sizeof(ctx->flc[0]); ++ + return 0; +} + @@ -17469,21 +17374,9 @@ index 00000000..102b0841 + +static void caam_exit_common(struct caam_ctx *ctx) +{ -+ int i; -+ -+ for (i = 0; i < NUM_OP; i++) { -+ if (!ctx->flc[i].flc_dma) -+ continue; -+ dma_unmap_single(ctx->dev, ctx->flc[i].flc_dma, -+ sizeof(ctx->flc[i].flc) + -+ desc_bytes(ctx->flc[i].sh_desc), -+ DMA_TO_DEVICE); -+ } -+ -+ if (ctx->key_dma) -+ dma_unmap_single(ctx->dev, ctx->key_dma, -+ ctx->cdata.keylen + ctx->adata.keylen_pad, -+ DMA_TO_DEVICE); ++ dma_unmap_single_attrs(ctx->dev, ctx->flc_dma[0], ++ offsetof(struct caam_ctx, flc_dma), ++ DMA_BIDIRECTIONAL, DMA_ATTR_SKIP_CPU_SYNC); +} + +static void caam_cra_exit(struct crypto_tfm *tfm) @@ -18852,17 +18745,1701 @@ index 00000000..102b0841 + alg->exit = caam_cra_exit_aead; +} + -+static void dpaa2_caam_fqdan_cb(struct dpaa2_io_notification_ctx *nctx) -+{ -+ struct dpaa2_caam_priv_per_cpu *ppriv; ++/* max hash key is max split key size */ ++#define CAAM_MAX_HASH_KEY_SIZE (SHA512_DIGEST_SIZE * 2) + -+ ppriv = container_of(nctx, struct dpaa2_caam_priv_per_cpu, nctx); -+ napi_schedule_irqoff(&ppriv->napi); -+} ++#define CAAM_MAX_HASH_BLOCK_SIZE SHA512_BLOCK_SIZE ++#define CAAM_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE + -+static int __cold dpaa2_dpseci_dpio_setup(struct dpaa2_caam_priv *priv) -+{ -+ struct device *dev = priv->dev; ++#define DESC_HASH_MAX_USED_BYTES (DESC_AHASH_FINAL_LEN + \ ++ CAAM_MAX_HASH_KEY_SIZE) ++#define DESC_HASH_MAX_USED_LEN (DESC_HASH_MAX_USED_BYTES / CAAM_CMD_SZ) ++ ++/* caam context sizes for hashes: running digest + 8 */ ++#define HASH_MSG_LEN 8 ++#define MAX_CTX_LEN (HASH_MSG_LEN + SHA512_DIGEST_SIZE) ++ ++enum hash_optype { ++ UPDATE = 0, ++ UPDATE_FIRST, ++ FINALIZE, ++ DIGEST, ++ HASH_NUM_OP ++}; ++ ++/** ++ * caam_hash_ctx - ahash per-session context ++ * @flc: Flow Contexts array ++ * @flc_dma: I/O virtual addresses of the Flow Contexts ++ * @key: virtual address of the authentication key ++ * @dev: dpseci device ++ * @ctx_len: size of Context Register ++ * @adata: hashing algorithm details ++ */ ++struct caam_hash_ctx { ++ struct caam_flc flc[HASH_NUM_OP]; ++ dma_addr_t flc_dma[HASH_NUM_OP]; ++ u8 key[CAAM_MAX_HASH_KEY_SIZE]; ++ struct device *dev; ++ int ctx_len; ++ struct alginfo adata; ++}; ++ ++/* ahash state */ ++struct caam_hash_state { ++ struct caam_request caam_req; ++ dma_addr_t buf_dma; ++ dma_addr_t ctx_dma; ++ u8 buf_0[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned; ++ int buflen_0; ++ u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned; ++ int buflen_1; ++ u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned; ++ int (*update)(struct ahash_request *req); ++ int (*final)(struct ahash_request *req); ++ int (*finup)(struct ahash_request *req); ++ int current_buf; ++}; ++ ++struct caam_export_state { ++ u8 buf[CAAM_MAX_HASH_BLOCK_SIZE]; ++ u8 caam_ctx[MAX_CTX_LEN]; ++ int buflen; ++ int (*update)(struct ahash_request *req); ++ int (*final)(struct ahash_request *req); ++ int (*finup)(struct ahash_request *req); ++}; ++ ++static inline void switch_buf(struct caam_hash_state *state) ++{ ++ state->current_buf ^= 1; ++} ++ ++static inline u8 *current_buf(struct caam_hash_state *state) ++{ ++ return state->current_buf ? state->buf_1 : state->buf_0; ++} ++ ++static inline u8 *alt_buf(struct caam_hash_state *state) ++{ ++ return state->current_buf ? state->buf_0 : state->buf_1; ++} ++ ++static inline int *current_buflen(struct caam_hash_state *state) ++{ ++ return state->current_buf ? &state->buflen_1 : &state->buflen_0; ++} ++ ++static inline int *alt_buflen(struct caam_hash_state *state) ++{ ++ return state->current_buf ? &state->buflen_0 : &state->buflen_1; ++} ++ ++/* Map current buffer in state (if length > 0) and put it in link table */ ++static inline int buf_map_to_qm_sg(struct device *dev, ++ struct dpaa2_sg_entry *qm_sg, ++ struct caam_hash_state *state) ++{ ++ int buflen = *current_buflen(state); ++ ++ if (!buflen) ++ return 0; ++ ++ state->buf_dma = dma_map_single(dev, current_buf(state), buflen, ++ DMA_TO_DEVICE); ++ if (dma_mapping_error(dev, state->buf_dma)) { ++ dev_err(dev, "unable to map buf\n"); ++ state->buf_dma = 0; ++ return -ENOMEM; ++ } ++ ++ dma_to_qm_sg_one(qm_sg, state->buf_dma, buflen, 0); ++ ++ return 0; ++} ++ ++/* Map state->caam_ctx, and add it to link table */ ++static inline int ctx_map_to_qm_sg(struct device *dev, ++ struct caam_hash_state *state, int ctx_len, ++ struct dpaa2_sg_entry *qm_sg, u32 flag) ++{ ++ state->ctx_dma = dma_map_single(dev, state->caam_ctx, ctx_len, flag); ++ if (dma_mapping_error(dev, state->ctx_dma)) { ++ dev_err(dev, "unable to map ctx\n"); ++ state->ctx_dma = 0; ++ return -ENOMEM; ++ } ++ ++ dma_to_qm_sg_one(qm_sg, state->ctx_dma, ctx_len, 0); ++ ++ return 0; ++} ++ ++static int ahash_set_sh_desc(struct crypto_ahash *ahash) ++{ ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ int digestsize = crypto_ahash_digestsize(ahash); ++ struct dpaa2_caam_priv *priv = dev_get_drvdata(ctx->dev); ++ struct caam_flc *flc; ++ u32 *desc; ++ ++ ctx->adata.key_virt = ctx->key; ++ ctx->adata.key_inline = true; ++ ++ /* ahash_update shared descriptor */ ++ flc = &ctx->flc[UPDATE]; ++ desc = flc->sh_desc; ++ cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_UPDATE, ctx->ctx_len, ++ ctx->ctx_len, true, priv->sec_attr.era); ++ flc->flc[1] = desc_len(desc); /* SDL */ ++ dma_sync_single_for_device(ctx->dev, ctx->flc_dma[UPDATE], ++ desc_bytes(desc), DMA_BIDIRECTIONAL); ++#ifdef DEBUG ++ print_hex_dump(KERN_ERR, ++ "ahash update shdesc@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); ++#endif ++ ++ /* ahash_update_first shared descriptor */ ++ flc = &ctx->flc[UPDATE_FIRST]; ++ desc = flc->sh_desc; ++ cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INIT, ctx->ctx_len, ++ ctx->ctx_len, false, priv->sec_attr.era); ++ flc->flc[1] = desc_len(desc); /* SDL */ ++ dma_sync_single_for_device(ctx->dev, ctx->flc_dma[UPDATE_FIRST], ++ desc_bytes(desc), DMA_BIDIRECTIONAL); ++#ifdef DEBUG ++ print_hex_dump(KERN_ERR, ++ "ahash update first shdesc@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); ++#endif ++ ++ /* ahash_final shared descriptor */ ++ flc = &ctx->flc[FINALIZE]; ++ desc = flc->sh_desc; ++ cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_FINALIZE, digestsize, ++ ctx->ctx_len, true, priv->sec_attr.era); ++ flc->flc[1] = desc_len(desc); /* SDL */ ++ dma_sync_single_for_device(ctx->dev, ctx->flc_dma[FINALIZE], ++ desc_bytes(desc), DMA_BIDIRECTIONAL); ++#ifdef DEBUG ++ print_hex_dump(KERN_ERR, ++ "ahash final shdesc@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); ++#endif ++ ++ /* ahash_digest shared descriptor */ ++ flc = &ctx->flc[DIGEST]; ++ desc = flc->sh_desc; ++ cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INITFINAL, digestsize, ++ ctx->ctx_len, false, priv->sec_attr.era); ++ flc->flc[1] = desc_len(desc); /* SDL */ ++ dma_sync_single_for_device(ctx->dev, ctx->flc_dma[DIGEST], ++ desc_bytes(desc), DMA_BIDIRECTIONAL); ++#ifdef DEBUG ++ print_hex_dump(KERN_ERR, ++ "ahash digest shdesc@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); ++#endif ++ ++ return 0; ++} ++ ++/* Digest hash size if it is too large */ ++static int hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in, ++ u32 *keylen, u8 *key_out, u32 digestsize) ++{ ++ struct caam_request *req_ctx; ++ u32 *desc; ++ struct split_key_sh_result result; ++ dma_addr_t src_dma, dst_dma; ++ struct caam_flc *flc; ++ dma_addr_t flc_dma; ++ int ret = -ENOMEM; ++ struct dpaa2_fl_entry *in_fle, *out_fle; ++ ++ req_ctx = kzalloc(sizeof(*req_ctx), GFP_KERNEL | GFP_DMA); ++ if (!req_ctx) ++ return -ENOMEM; ++ ++ in_fle = &req_ctx->fd_flt[1]; ++ out_fle = &req_ctx->fd_flt[0]; ++ ++ flc = kzalloc(sizeof(*flc), GFP_KERNEL | GFP_DMA); ++ if (!flc) ++ goto err_flc; ++ ++ src_dma = dma_map_single(ctx->dev, (void *)key_in, *keylen, ++ DMA_TO_DEVICE); ++ if (dma_mapping_error(ctx->dev, src_dma)) { ++ dev_err(ctx->dev, "unable to map key input memory\n"); ++ goto err_src_dma; ++ } ++ dst_dma = dma_map_single(ctx->dev, (void *)key_out, digestsize, ++ DMA_FROM_DEVICE); ++ if (dma_mapping_error(ctx->dev, dst_dma)) { ++ dev_err(ctx->dev, "unable to map key output memory\n"); ++ goto err_dst_dma; ++ } ++ ++ desc = flc->sh_desc; ++ ++ init_sh_desc(desc, 0); ++ ++ /* descriptor to perform unkeyed hash on key_in */ ++ append_operation(desc, ctx->adata.algtype | OP_ALG_ENCRYPT | ++ OP_ALG_AS_INITFINAL); ++ append_seq_fifo_load(desc, *keylen, FIFOLD_CLASS_CLASS2 | ++ FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_MSG); ++ append_seq_store(desc, digestsize, LDST_CLASS_2_CCB | ++ LDST_SRCDST_BYTE_CONTEXT); ++ ++ flc->flc[1] = desc_len(desc); /* SDL */ ++ flc_dma = dma_map_single(ctx->dev, flc, sizeof(flc->flc) + ++ desc_bytes(desc), DMA_TO_DEVICE); ++ if (dma_mapping_error(ctx->dev, flc_dma)) { ++ dev_err(ctx->dev, "unable to map shared descriptor\n"); ++ goto err_flc_dma; ++ } ++ ++ dpaa2_fl_set_final(in_fle, true); ++ dpaa2_fl_set_format(in_fle, dpaa2_fl_single); ++ dpaa2_fl_set_addr(in_fle, src_dma); ++ dpaa2_fl_set_len(in_fle, *keylen); ++ dpaa2_fl_set_format(out_fle, dpaa2_fl_single); ++ dpaa2_fl_set_addr(out_fle, dst_dma); ++ dpaa2_fl_set_len(out_fle, digestsize); ++ ++#ifdef DEBUG ++ print_hex_dump(KERN_ERR, "key_in@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, key_in, *keylen, 1); ++ print_hex_dump(KERN_ERR, "shdesc@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); ++#endif ++ ++ result.err = 0; ++ init_completion(&result.completion); ++ result.dev = ctx->dev; ++ ++ req_ctx->flc = flc; ++ req_ctx->flc_dma = flc_dma; ++ req_ctx->cbk = split_key_sh_done; ++ req_ctx->ctx = &result; ++ ++ ret = dpaa2_caam_enqueue(ctx->dev, req_ctx); ++ if (ret == -EINPROGRESS) { ++ /* in progress */ ++ wait_for_completion(&result.completion); ++ ret = result.err; ++#ifdef DEBUG ++ print_hex_dump(KERN_ERR, ++ "digested key@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, key_in, digestsize, ++ 1); ++#endif ++ } ++ ++ dma_unmap_single(ctx->dev, flc_dma, sizeof(flc->flc) + desc_bytes(desc), ++ DMA_TO_DEVICE); ++err_flc_dma: ++ dma_unmap_single(ctx->dev, dst_dma, digestsize, DMA_FROM_DEVICE); ++err_dst_dma: ++ dma_unmap_single(ctx->dev, src_dma, *keylen, DMA_TO_DEVICE); ++err_src_dma: ++ kfree(flc); ++err_flc: ++ kfree(req_ctx); ++ ++ *keylen = digestsize; ++ ++ return ret; ++} ++ ++static int ahash_setkey(struct crypto_ahash *ahash, const u8 *key, ++ unsigned int keylen) ++{ ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ unsigned int blocksize = crypto_tfm_alg_blocksize(&ahash->base); ++ unsigned int digestsize = crypto_ahash_digestsize(ahash); ++ int ret; ++ u8 *hashed_key = NULL; ++ ++#ifdef DEBUG ++ dev_err(ctx->dev, "keylen %d blocksize %d\n", keylen, blocksize); ++#endif ++ ++ if (keylen > blocksize) { ++ hashed_key = kmalloc_array(digestsize, sizeof(*hashed_key), ++ GFP_KERNEL | GFP_DMA); ++ if (!hashed_key) ++ return -ENOMEM; ++ ret = hash_digest_key(ctx, key, &keylen, hashed_key, ++ digestsize); ++ if (ret) ++ goto bad_free_key; ++ key = hashed_key; ++ } ++ ++ ctx->adata.keylen = keylen; ++ ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & ++ OP_ALG_ALGSEL_MASK); ++ if (ctx->adata.keylen_pad > CAAM_MAX_HASH_KEY_SIZE) ++ goto bad_free_key; ++ ++ memcpy(ctx->key, key, keylen); ++ ++ kfree(hashed_key); ++ return ahash_set_sh_desc(ahash); ++bad_free_key: ++ kfree(hashed_key); ++ crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN); ++ return -EINVAL; ++} ++ ++static inline void ahash_unmap(struct device *dev, struct ahash_edesc *edesc, ++ struct ahash_request *req, int dst_len) ++{ ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ ++ if (edesc->src_nents) ++ dma_unmap_sg(dev, req->src, edesc->src_nents, DMA_TO_DEVICE); ++ if (edesc->dst_dma) ++ dma_unmap_single(dev, edesc->dst_dma, dst_len, DMA_FROM_DEVICE); ++ ++ if (edesc->qm_sg_bytes) ++ dma_unmap_single(dev, edesc->qm_sg_dma, edesc->qm_sg_bytes, ++ DMA_TO_DEVICE); ++ ++ if (state->buf_dma) { ++ dma_unmap_single(dev, state->buf_dma, *current_buflen(state), ++ DMA_TO_DEVICE); ++ state->buf_dma = 0; ++ } ++} ++ ++static inline void ahash_unmap_ctx(struct device *dev, ++ struct ahash_edesc *edesc, ++ struct ahash_request *req, int dst_len, ++ u32 flag) ++{ ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ ++ if (state->ctx_dma) { ++ dma_unmap_single(dev, state->ctx_dma, ctx->ctx_len, flag); ++ state->ctx_dma = 0; ++ } ++ ahash_unmap(dev, edesc, req, dst_len); ++} ++ ++static void ahash_done(void *cbk_ctx, u32 status) ++{ ++ struct crypto_async_request *areq = cbk_ctx; ++ struct ahash_request *req = ahash_request_cast(areq); ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ struct ahash_edesc *edesc = state->caam_req.edesc; ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ int digestsize = crypto_ahash_digestsize(ahash); ++ int ecode = 0; ++ ++#ifdef DEBUG ++ dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status); ++#endif ++ ++ if (unlikely(status)) { ++ caam_qi2_strstatus(ctx->dev, status); ++ ecode = -EIO; ++ } ++ ++ ahash_unmap(ctx->dev, edesc, req, digestsize); ++ qi_cache_free(edesc); ++ ++#ifdef DEBUG ++ print_hex_dump(KERN_ERR, "ctx@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx, ++ ctx->ctx_len, 1); ++ if (req->result) ++ print_hex_dump(KERN_ERR, "result@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, req->result, ++ digestsize, 1); ++#endif ++ ++ req->base.complete(&req->base, ecode); ++} ++ ++static void ahash_done_bi(void *cbk_ctx, u32 status) ++{ ++ struct crypto_async_request *areq = cbk_ctx; ++ struct ahash_request *req = ahash_request_cast(areq); ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ struct ahash_edesc *edesc = state->caam_req.edesc; ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ int ecode = 0; ++#ifdef DEBUG ++ int digestsize = crypto_ahash_digestsize(ahash); ++ ++ dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status); ++#endif ++ ++ if (unlikely(status)) { ++ caam_qi2_strstatus(ctx->dev, status); ++ ecode = -EIO; ++ } ++ ++ ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL); ++ switch_buf(state); ++ qi_cache_free(edesc); ++ ++#ifdef DEBUG ++ print_hex_dump(KERN_ERR, "ctx@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx, ++ ctx->ctx_len, 1); ++ if (req->result) ++ print_hex_dump(KERN_ERR, "result@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, req->result, ++ digestsize, 1); ++#endif ++ ++ req->base.complete(&req->base, ecode); ++} ++ ++static void ahash_done_ctx_src(void *cbk_ctx, u32 status) ++{ ++ struct crypto_async_request *areq = cbk_ctx; ++ struct ahash_request *req = ahash_request_cast(areq); ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ struct ahash_edesc *edesc = state->caam_req.edesc; ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ int digestsize = crypto_ahash_digestsize(ahash); ++ int ecode = 0; ++ ++#ifdef DEBUG ++ dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status); ++#endif ++ ++ if (unlikely(status)) { ++ caam_qi2_strstatus(ctx->dev, status); ++ ecode = -EIO; ++ } ++ ++ ahash_unmap_ctx(ctx->dev, edesc, req, digestsize, DMA_TO_DEVICE); ++ qi_cache_free(edesc); ++ ++#ifdef DEBUG ++ print_hex_dump(KERN_ERR, "ctx@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx, ++ ctx->ctx_len, 1); ++ if (req->result) ++ print_hex_dump(KERN_ERR, "result@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, req->result, ++ digestsize, 1); ++#endif ++ ++ req->base.complete(&req->base, ecode); ++} ++ ++static void ahash_done_ctx_dst(void *cbk_ctx, u32 status) ++{ ++ struct crypto_async_request *areq = cbk_ctx; ++ struct ahash_request *req = ahash_request_cast(areq); ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ struct ahash_edesc *edesc = state->caam_req.edesc; ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ int ecode = 0; ++#ifdef DEBUG ++ int digestsize = crypto_ahash_digestsize(ahash); ++ ++ dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status); ++#endif ++ ++ if (unlikely(status)) { ++ caam_qi2_strstatus(ctx->dev, status); ++ ecode = -EIO; ++ } ++ ++ ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_FROM_DEVICE); ++ switch_buf(state); ++ qi_cache_free(edesc); ++ ++#ifdef DEBUG ++ print_hex_dump(KERN_ERR, "ctx@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx, ++ ctx->ctx_len, 1); ++ if (req->result) ++ print_hex_dump(KERN_ERR, "result@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, req->result, ++ digestsize, 1); ++#endif ++ ++ req->base.complete(&req->base, ecode); ++} ++ ++static int ahash_update_ctx(struct ahash_request *req) ++{ ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ struct caam_request *req_ctx = &state->caam_req; ++ struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1]; ++ struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0]; ++ gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? ++ GFP_KERNEL : GFP_ATOMIC; ++ u8 *buf = current_buf(state); ++ int *buflen = current_buflen(state); ++ u8 *next_buf = alt_buf(state); ++ int *next_buflen = alt_buflen(state), last_buflen; ++ int in_len = *buflen + req->nbytes, to_hash; ++ int src_nents, mapped_nents, qm_sg_bytes, qm_sg_src_index; ++ struct ahash_edesc *edesc; ++ int ret = 0; ++ ++ last_buflen = *next_buflen; ++ *next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1); ++ to_hash = in_len - *next_buflen; ++ ++ if (to_hash) { ++ struct dpaa2_sg_entry *sg_table; ++ ++ src_nents = sg_nents_for_len(req->src, ++ req->nbytes - (*next_buflen)); ++ if (src_nents < 0) { ++ dev_err(ctx->dev, "Invalid number of src SG.\n"); ++ return src_nents; ++ } ++ ++ if (src_nents) { ++ mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents, ++ DMA_TO_DEVICE); ++ if (!mapped_nents) { ++ dev_err(ctx->dev, "unable to DMA map source\n"); ++ return -ENOMEM; ++ } ++ } else { ++ mapped_nents = 0; ++ } ++ ++ /* allocate space for base edesc and link tables */ ++ edesc = qi_cache_zalloc(GFP_DMA | flags); ++ if (!edesc) { ++ dma_unmap_sg(ctx->dev, req->src, src_nents, ++ DMA_TO_DEVICE); ++ return -ENOMEM; ++ } ++ ++ edesc->src_nents = src_nents; ++ qm_sg_src_index = 1 + (*buflen ? 1 : 0); ++ qm_sg_bytes = (qm_sg_src_index + mapped_nents) * ++ sizeof(*sg_table); ++ sg_table = &edesc->sgt[0]; ++ ++ ret = ctx_map_to_qm_sg(ctx->dev, state, ctx->ctx_len, sg_table, ++ DMA_BIDIRECTIONAL); ++ if (ret) ++ goto unmap_ctx; ++ ++ ret = buf_map_to_qm_sg(ctx->dev, sg_table + 1, state); ++ if (ret) ++ goto unmap_ctx; ++ ++ if (mapped_nents) { ++ sg_to_qm_sg_last(req->src, mapped_nents, ++ sg_table + qm_sg_src_index, 0); ++ if (*next_buflen) ++ scatterwalk_map_and_copy(next_buf, req->src, ++ to_hash - *buflen, ++ *next_buflen, 0); ++ } else { ++ dpaa2_sg_set_final(sg_table + qm_sg_src_index - 1, ++ true); ++ } ++ ++ edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, ++ qm_sg_bytes, DMA_TO_DEVICE); ++ if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) { ++ dev_err(ctx->dev, "unable to map S/G table\n"); ++ ret = -ENOMEM; ++ goto unmap_ctx; ++ } ++ edesc->qm_sg_bytes = qm_sg_bytes; ++ ++ memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt)); ++ dpaa2_fl_set_final(in_fle, true); ++ dpaa2_fl_set_format(in_fle, dpaa2_fl_sg); ++ dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma); ++ dpaa2_fl_set_len(in_fle, ctx->ctx_len + to_hash); ++ dpaa2_fl_set_format(out_fle, dpaa2_fl_single); ++ dpaa2_fl_set_addr(out_fle, state->ctx_dma); ++ dpaa2_fl_set_len(out_fle, ctx->ctx_len); ++ ++ req_ctx->flc = &ctx->flc[UPDATE]; ++ req_ctx->flc_dma = ctx->flc_dma[UPDATE]; ++ req_ctx->cbk = ahash_done_bi; ++ req_ctx->ctx = &req->base; ++ req_ctx->edesc = edesc; ++ ++ ret = dpaa2_caam_enqueue(ctx->dev, req_ctx); ++ if (ret != -EINPROGRESS && ++ !(ret == -EBUSY && ++ req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) ++ goto unmap_ctx; ++ } else if (*next_buflen) { ++ scatterwalk_map_and_copy(buf + *buflen, req->src, 0, ++ req->nbytes, 0); ++ *buflen = *next_buflen; ++ *next_buflen = last_buflen; ++ } ++#ifdef DEBUG ++ print_hex_dump(KERN_ERR, "buf@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1); ++ print_hex_dump(KERN_ERR, "next buf@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, next_buf, ++ *next_buflen, 1); ++#endif ++ ++ return ret; ++unmap_ctx: ++ ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL); ++ qi_cache_free(edesc); ++ return ret; ++} ++ ++static int ahash_final_ctx(struct ahash_request *req) ++{ ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ struct caam_request *req_ctx = &state->caam_req; ++ struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1]; ++ struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0]; ++ gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? ++ GFP_KERNEL : GFP_ATOMIC; ++ int buflen = *current_buflen(state); ++ int qm_sg_bytes, qm_sg_src_index; ++ int digestsize = crypto_ahash_digestsize(ahash); ++ struct ahash_edesc *edesc; ++ struct dpaa2_sg_entry *sg_table; ++ int ret; ++ ++ /* allocate space for base edesc and link tables */ ++ edesc = qi_cache_zalloc(GFP_DMA | flags); ++ if (!edesc) ++ return -ENOMEM; ++ ++ qm_sg_src_index = 1 + (buflen ? 1 : 0); ++ qm_sg_bytes = qm_sg_src_index * sizeof(*sg_table); ++ sg_table = &edesc->sgt[0]; ++ ++ ret = ctx_map_to_qm_sg(ctx->dev, state, ctx->ctx_len, sg_table, ++ DMA_TO_DEVICE); ++ if (ret) ++ goto unmap_ctx; ++ ++ ret = buf_map_to_qm_sg(ctx->dev, sg_table + 1, state); ++ if (ret) ++ goto unmap_ctx; ++ ++ dpaa2_sg_set_final(sg_table + qm_sg_src_index - 1, true); ++ ++ edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, qm_sg_bytes, ++ DMA_TO_DEVICE); ++ if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) { ++ dev_err(ctx->dev, "unable to map S/G table\n"); ++ ret = -ENOMEM; ++ goto unmap_ctx; ++ } ++ edesc->qm_sg_bytes = qm_sg_bytes; ++ ++ edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize, ++ DMA_FROM_DEVICE); ++ if (dma_mapping_error(ctx->dev, edesc->dst_dma)) { ++ dev_err(ctx->dev, "unable to map dst\n"); ++ edesc->dst_dma = 0; ++ ret = -ENOMEM; ++ goto unmap_ctx; ++ } ++ ++ memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt)); ++ dpaa2_fl_set_final(in_fle, true); ++ dpaa2_fl_set_format(in_fle, dpaa2_fl_sg); ++ dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma); ++ dpaa2_fl_set_len(in_fle, ctx->ctx_len + buflen); ++ dpaa2_fl_set_format(out_fle, dpaa2_fl_single); ++ dpaa2_fl_set_addr(out_fle, edesc->dst_dma); ++ dpaa2_fl_set_len(out_fle, digestsize); ++ ++ req_ctx->flc = &ctx->flc[FINALIZE]; ++ req_ctx->flc_dma = ctx->flc_dma[FINALIZE]; ++ req_ctx->cbk = ahash_done_ctx_src; ++ req_ctx->ctx = &req->base; ++ req_ctx->edesc = edesc; ++ ++ ret = dpaa2_caam_enqueue(ctx->dev, req_ctx); ++ if (ret == -EINPROGRESS || ++ (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) ++ return ret; ++ ++unmap_ctx: ++ ahash_unmap_ctx(ctx->dev, edesc, req, digestsize, DMA_FROM_DEVICE); ++ qi_cache_free(edesc); ++ return ret; ++} ++ ++static int ahash_finup_ctx(struct ahash_request *req) ++{ ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ struct caam_request *req_ctx = &state->caam_req; ++ struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1]; ++ struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0]; ++ gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? ++ GFP_KERNEL : GFP_ATOMIC; ++ int buflen = *current_buflen(state); ++ int qm_sg_bytes, qm_sg_src_index; ++ int src_nents, mapped_nents; ++ int digestsize = crypto_ahash_digestsize(ahash); ++ struct ahash_edesc *edesc; ++ struct dpaa2_sg_entry *sg_table; ++ int ret; ++ ++ src_nents = sg_nents_for_len(req->src, req->nbytes); ++ if (src_nents < 0) { ++ dev_err(ctx->dev, "Invalid number of src SG.\n"); ++ return src_nents; ++ } ++ ++ if (src_nents) { ++ mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents, ++ DMA_TO_DEVICE); ++ if (!mapped_nents) { ++ dev_err(ctx->dev, "unable to DMA map source\n"); ++ return -ENOMEM; ++ } ++ } else { ++ mapped_nents = 0; ++ } ++ ++ /* allocate space for base edesc and link tables */ ++ edesc = qi_cache_zalloc(GFP_DMA | flags); ++ if (!edesc) { ++ dma_unmap_sg(ctx->dev, req->src, src_nents, DMA_TO_DEVICE); ++ return -ENOMEM; ++ } ++ ++ edesc->src_nents = src_nents; ++ qm_sg_src_index = 1 + (buflen ? 1 : 0); ++ qm_sg_bytes = (qm_sg_src_index + mapped_nents) * sizeof(*sg_table); ++ sg_table = &edesc->sgt[0]; ++ ++ ret = ctx_map_to_qm_sg(ctx->dev, state, ctx->ctx_len, sg_table, ++ DMA_TO_DEVICE); ++ if (ret) ++ goto unmap_ctx; ++ ++ ret = buf_map_to_qm_sg(ctx->dev, sg_table + 1, state); ++ if (ret) ++ goto unmap_ctx; ++ ++ sg_to_qm_sg_last(req->src, mapped_nents, sg_table + qm_sg_src_index, 0); ++ ++ edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, qm_sg_bytes, ++ DMA_TO_DEVICE); ++ if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) { ++ dev_err(ctx->dev, "unable to map S/G table\n"); ++ ret = -ENOMEM; ++ goto unmap_ctx; ++ } ++ edesc->qm_sg_bytes = qm_sg_bytes; ++ ++ edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize, ++ DMA_FROM_DEVICE); ++ if (dma_mapping_error(ctx->dev, edesc->dst_dma)) { ++ dev_err(ctx->dev, "unable to map dst\n"); ++ edesc->dst_dma = 0; ++ ret = -ENOMEM; ++ goto unmap_ctx; ++ } ++ ++ memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt)); ++ dpaa2_fl_set_final(in_fle, true); ++ dpaa2_fl_set_format(in_fle, dpaa2_fl_sg); ++ dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma); ++ dpaa2_fl_set_len(in_fle, ctx->ctx_len + buflen + req->nbytes); ++ dpaa2_fl_set_format(out_fle, dpaa2_fl_single); ++ dpaa2_fl_set_addr(out_fle, edesc->dst_dma); ++ dpaa2_fl_set_len(out_fle, digestsize); ++ ++ req_ctx->flc = &ctx->flc[FINALIZE]; ++ req_ctx->flc_dma = ctx->flc_dma[FINALIZE]; ++ req_ctx->cbk = ahash_done_ctx_src; ++ req_ctx->ctx = &req->base; ++ req_ctx->edesc = edesc; ++ ++ ret = dpaa2_caam_enqueue(ctx->dev, req_ctx); ++ if (ret == -EINPROGRESS || ++ (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) ++ return ret; ++ ++unmap_ctx: ++ ahash_unmap_ctx(ctx->dev, edesc, req, digestsize, DMA_FROM_DEVICE); ++ qi_cache_free(edesc); ++ return ret; ++} ++ ++static int ahash_digest(struct ahash_request *req) ++{ ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ struct caam_request *req_ctx = &state->caam_req; ++ struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1]; ++ struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0]; ++ gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? ++ GFP_KERNEL : GFP_ATOMIC; ++ int digestsize = crypto_ahash_digestsize(ahash); ++ int src_nents, mapped_nents; ++ struct ahash_edesc *edesc; ++ int ret = -ENOMEM; ++ ++ state->buf_dma = 0; ++ ++ src_nents = sg_nents_for_len(req->src, req->nbytes); ++ if (src_nents < 0) { ++ dev_err(ctx->dev, "Invalid number of src SG.\n"); ++ return src_nents; ++ } ++ ++ if (src_nents) { ++ mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents, ++ DMA_TO_DEVICE); ++ if (!mapped_nents) { ++ dev_err(ctx->dev, "unable to map source for DMA\n"); ++ return ret; ++ } ++ } else { ++ mapped_nents = 0; ++ } ++ ++ /* allocate space for base edesc and link tables */ ++ edesc = qi_cache_zalloc(GFP_DMA | flags); ++ if (!edesc) { ++ dma_unmap_sg(ctx->dev, req->src, src_nents, DMA_TO_DEVICE); ++ return ret; ++ } ++ ++ edesc->src_nents = src_nents; ++ memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt)); ++ ++ if (mapped_nents > 1) { ++ int qm_sg_bytes; ++ struct dpaa2_sg_entry *sg_table = &edesc->sgt[0]; ++ ++ qm_sg_bytes = mapped_nents * sizeof(*sg_table); ++ sg_to_qm_sg_last(req->src, mapped_nents, sg_table, 0); ++ edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, ++ qm_sg_bytes, DMA_TO_DEVICE); ++ if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) { ++ dev_err(ctx->dev, "unable to map S/G table\n"); ++ goto unmap; ++ } ++ edesc->qm_sg_bytes = qm_sg_bytes; ++ dpaa2_fl_set_format(in_fle, dpaa2_fl_sg); ++ dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma); ++ } else { ++ dpaa2_fl_set_format(in_fle, dpaa2_fl_single); ++ dpaa2_fl_set_addr(in_fle, sg_dma_address(req->src)); ++ } ++ ++ edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize, ++ DMA_FROM_DEVICE); ++ if (dma_mapping_error(ctx->dev, edesc->dst_dma)) { ++ dev_err(ctx->dev, "unable to map dst\n"); ++ edesc->dst_dma = 0; ++ goto unmap; ++ } ++ ++ dpaa2_fl_set_final(in_fle, true); ++ dpaa2_fl_set_len(in_fle, req->nbytes); ++ dpaa2_fl_set_format(out_fle, dpaa2_fl_single); ++ dpaa2_fl_set_addr(out_fle, edesc->dst_dma); ++ dpaa2_fl_set_len(out_fle, digestsize); ++ ++ req_ctx->flc = &ctx->flc[DIGEST]; ++ req_ctx->flc_dma = ctx->flc_dma[DIGEST]; ++ req_ctx->cbk = ahash_done; ++ req_ctx->ctx = &req->base; ++ req_ctx->edesc = edesc; ++ ret = dpaa2_caam_enqueue(ctx->dev, req_ctx); ++ if (ret == -EINPROGRESS || ++ (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) ++ return ret; ++ ++unmap: ++ ahash_unmap(ctx->dev, edesc, req, digestsize); ++ qi_cache_free(edesc); ++ return ret; ++} ++ ++static int ahash_final_no_ctx(struct ahash_request *req) ++{ ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ struct caam_request *req_ctx = &state->caam_req; ++ struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1]; ++ struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0]; ++ gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? ++ GFP_KERNEL : GFP_ATOMIC; ++ u8 *buf = current_buf(state); ++ int buflen = *current_buflen(state); ++ int digestsize = crypto_ahash_digestsize(ahash); ++ struct ahash_edesc *edesc; ++ int ret = -ENOMEM; ++ ++ /* allocate space for base edesc and link tables */ ++ edesc = qi_cache_zalloc(GFP_DMA | flags); ++ if (!edesc) ++ return ret; ++ ++ state->buf_dma = dma_map_single(ctx->dev, buf, buflen, DMA_TO_DEVICE); ++ if (dma_mapping_error(ctx->dev, state->buf_dma)) { ++ dev_err(ctx->dev, "unable to map src\n"); ++ goto unmap; ++ } ++ ++ edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize, ++ DMA_FROM_DEVICE); ++ if (dma_mapping_error(ctx->dev, edesc->dst_dma)) { ++ dev_err(ctx->dev, "unable to map dst\n"); ++ edesc->dst_dma = 0; ++ goto unmap; ++ } ++ ++ memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt)); ++ dpaa2_fl_set_final(in_fle, true); ++ dpaa2_fl_set_format(in_fle, dpaa2_fl_single); ++ dpaa2_fl_set_addr(in_fle, state->buf_dma); ++ dpaa2_fl_set_len(in_fle, buflen); ++ dpaa2_fl_set_format(out_fle, dpaa2_fl_single); ++ dpaa2_fl_set_addr(out_fle, edesc->dst_dma); ++ dpaa2_fl_set_len(out_fle, digestsize); ++ ++ req_ctx->flc = &ctx->flc[DIGEST]; ++ req_ctx->flc_dma = ctx->flc_dma[DIGEST]; ++ req_ctx->cbk = ahash_done; ++ req_ctx->ctx = &req->base; ++ req_ctx->edesc = edesc; ++ ++ ret = dpaa2_caam_enqueue(ctx->dev, req_ctx); ++ if (ret == -EINPROGRESS || ++ (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) ++ return ret; ++ ++unmap: ++ ahash_unmap(ctx->dev, edesc, req, digestsize); ++ qi_cache_free(edesc); ++ return ret; ++} ++ ++static int ahash_update_no_ctx(struct ahash_request *req) ++{ ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ struct caam_request *req_ctx = &state->caam_req; ++ struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1]; ++ struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0]; ++ gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? ++ GFP_KERNEL : GFP_ATOMIC; ++ u8 *buf = current_buf(state); ++ int *buflen = current_buflen(state); ++ u8 *next_buf = alt_buf(state); ++ int *next_buflen = alt_buflen(state); ++ int in_len = *buflen + req->nbytes, to_hash; ++ int qm_sg_bytes, src_nents, mapped_nents; ++ struct ahash_edesc *edesc; ++ int ret = 0; ++ ++ *next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1); ++ to_hash = in_len - *next_buflen; ++ ++ if (to_hash) { ++ struct dpaa2_sg_entry *sg_table; ++ ++ src_nents = sg_nents_for_len(req->src, ++ req->nbytes - *next_buflen); ++ if (src_nents < 0) { ++ dev_err(ctx->dev, "Invalid number of src SG.\n"); ++ return src_nents; ++ } ++ ++ if (src_nents) { ++ mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents, ++ DMA_TO_DEVICE); ++ if (!mapped_nents) { ++ dev_err(ctx->dev, "unable to DMA map source\n"); ++ return -ENOMEM; ++ } ++ } else { ++ mapped_nents = 0; ++ } ++ ++ /* allocate space for base edesc and link tables */ ++ edesc = qi_cache_zalloc(GFP_DMA | flags); ++ if (!edesc) { ++ dma_unmap_sg(ctx->dev, req->src, src_nents, ++ DMA_TO_DEVICE); ++ return -ENOMEM; ++ } ++ ++ edesc->src_nents = src_nents; ++ qm_sg_bytes = (1 + mapped_nents) * sizeof(*sg_table); ++ sg_table = &edesc->sgt[0]; ++ ++ ret = buf_map_to_qm_sg(ctx->dev, sg_table, state); ++ if (ret) ++ goto unmap_ctx; ++ ++ sg_to_qm_sg_last(req->src, mapped_nents, sg_table + 1, 0); ++ ++ if (*next_buflen) ++ scatterwalk_map_and_copy(next_buf, req->src, ++ to_hash - *buflen, ++ *next_buflen, 0); ++ ++ edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, ++ qm_sg_bytes, DMA_TO_DEVICE); ++ if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) { ++ dev_err(ctx->dev, "unable to map S/G table\n"); ++ ret = -ENOMEM; ++ goto unmap_ctx; ++ } ++ edesc->qm_sg_bytes = qm_sg_bytes; ++ ++ state->ctx_dma = dma_map_single(ctx->dev, state->caam_ctx, ++ ctx->ctx_len, DMA_FROM_DEVICE); ++ if (dma_mapping_error(ctx->dev, state->ctx_dma)) { ++ dev_err(ctx->dev, "unable to map ctx\n"); ++ state->ctx_dma = 0; ++ ret = -ENOMEM; ++ goto unmap_ctx; ++ } ++ ++ memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt)); ++ dpaa2_fl_set_final(in_fle, true); ++ dpaa2_fl_set_format(in_fle, dpaa2_fl_sg); ++ dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma); ++ dpaa2_fl_set_len(in_fle, to_hash); ++ dpaa2_fl_set_format(out_fle, dpaa2_fl_single); ++ dpaa2_fl_set_addr(out_fle, state->ctx_dma); ++ dpaa2_fl_set_len(out_fle, ctx->ctx_len); ++ ++ req_ctx->flc = &ctx->flc[UPDATE_FIRST]; ++ req_ctx->flc_dma = ctx->flc_dma[UPDATE_FIRST]; ++ req_ctx->cbk = ahash_done_ctx_dst; ++ req_ctx->ctx = &req->base; ++ req_ctx->edesc = edesc; ++ ++ ret = dpaa2_caam_enqueue(ctx->dev, req_ctx); ++ if (ret != -EINPROGRESS && ++ !(ret == -EBUSY && ++ req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) ++ goto unmap_ctx; ++ ++ state->update = ahash_update_ctx; ++ state->finup = ahash_finup_ctx; ++ state->final = ahash_final_ctx; ++ } else if (*next_buflen) { ++ scatterwalk_map_and_copy(buf + *buflen, req->src, 0, ++ req->nbytes, 0); ++ *buflen = *next_buflen; ++ *next_buflen = 0; ++ } ++#ifdef DEBUG ++ print_hex_dump(KERN_ERR, "buf@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1); ++ print_hex_dump(KERN_ERR, "next buf@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, next_buf, ++ *next_buflen, 1); ++#endif ++ ++ return ret; ++unmap_ctx: ++ ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE); ++ qi_cache_free(edesc); ++ return ret; ++} ++ ++static int ahash_finup_no_ctx(struct ahash_request *req) ++{ ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ struct caam_request *req_ctx = &state->caam_req; ++ struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1]; ++ struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0]; ++ gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? ++ GFP_KERNEL : GFP_ATOMIC; ++ int buflen = *current_buflen(state); ++ int qm_sg_bytes, src_nents, mapped_nents; ++ int digestsize = crypto_ahash_digestsize(ahash); ++ struct ahash_edesc *edesc; ++ struct dpaa2_sg_entry *sg_table; ++ int ret; ++ ++ src_nents = sg_nents_for_len(req->src, req->nbytes); ++ if (src_nents < 0) { ++ dev_err(ctx->dev, "Invalid number of src SG.\n"); ++ return src_nents; ++ } ++ ++ if (src_nents) { ++ mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents, ++ DMA_TO_DEVICE); ++ if (!mapped_nents) { ++ dev_err(ctx->dev, "unable to DMA map source\n"); ++ return -ENOMEM; ++ } ++ } else { ++ mapped_nents = 0; ++ } ++ ++ /* allocate space for base edesc and link tables */ ++ edesc = qi_cache_zalloc(GFP_DMA | flags); ++ if (!edesc) { ++ dma_unmap_sg(ctx->dev, req->src, src_nents, DMA_TO_DEVICE); ++ return -ENOMEM; ++ } ++ ++ edesc->src_nents = src_nents; ++ qm_sg_bytes = (2 + mapped_nents) * sizeof(*sg_table); ++ sg_table = &edesc->sgt[0]; ++ ++ ret = buf_map_to_qm_sg(ctx->dev, sg_table, state); ++ if (ret) ++ goto unmap; ++ ++ sg_to_qm_sg_last(req->src, mapped_nents, sg_table + 1, 0); ++ ++ edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, qm_sg_bytes, ++ DMA_TO_DEVICE); ++ if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) { ++ dev_err(ctx->dev, "unable to map S/G table\n"); ++ ret = -ENOMEM; ++ goto unmap; ++ } ++ edesc->qm_sg_bytes = qm_sg_bytes; ++ ++ edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize, ++ DMA_FROM_DEVICE); ++ if (dma_mapping_error(ctx->dev, edesc->dst_dma)) { ++ dev_err(ctx->dev, "unable to map dst\n"); ++ edesc->dst_dma = 0; ++ ret = -ENOMEM; ++ goto unmap; ++ } ++ ++ memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt)); ++ dpaa2_fl_set_final(in_fle, true); ++ dpaa2_fl_set_format(in_fle, dpaa2_fl_sg); ++ dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma); ++ dpaa2_fl_set_len(in_fle, buflen + req->nbytes); ++ dpaa2_fl_set_format(out_fle, dpaa2_fl_single); ++ dpaa2_fl_set_addr(out_fle, edesc->dst_dma); ++ dpaa2_fl_set_len(out_fle, digestsize); ++ ++ req_ctx->flc = &ctx->flc[DIGEST]; ++ req_ctx->flc_dma = ctx->flc_dma[DIGEST]; ++ req_ctx->cbk = ahash_done; ++ req_ctx->ctx = &req->base; ++ req_ctx->edesc = edesc; ++ ret = dpaa2_caam_enqueue(ctx->dev, req_ctx); ++ if (ret != -EINPROGRESS && ++ !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) ++ goto unmap; ++ ++ return ret; ++unmap: ++ ahash_unmap(ctx->dev, edesc, req, digestsize); ++ qi_cache_free(edesc); ++ return -ENOMEM; ++} ++ ++static int ahash_update_first(struct ahash_request *req) ++{ ++ struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); ++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ struct caam_request *req_ctx = &state->caam_req; ++ struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1]; ++ struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0]; ++ gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? ++ GFP_KERNEL : GFP_ATOMIC; ++ u8 *next_buf = alt_buf(state); ++ int *next_buflen = alt_buflen(state); ++ int to_hash; ++ int src_nents, mapped_nents; ++ struct ahash_edesc *edesc; ++ int ret = 0; ++ ++ *next_buflen = req->nbytes & (crypto_tfm_alg_blocksize(&ahash->base) - ++ 1); ++ to_hash = req->nbytes - *next_buflen; ++ ++ if (to_hash) { ++ struct dpaa2_sg_entry *sg_table; ++ ++ src_nents = sg_nents_for_len(req->src, ++ req->nbytes - (*next_buflen)); ++ if (src_nents < 0) { ++ dev_err(ctx->dev, "Invalid number of src SG.\n"); ++ return src_nents; ++ } ++ ++ if (src_nents) { ++ mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents, ++ DMA_TO_DEVICE); ++ if (!mapped_nents) { ++ dev_err(ctx->dev, "unable to map source for DMA\n"); ++ return -ENOMEM; ++ } ++ } else { ++ mapped_nents = 0; ++ } ++ ++ /* allocate space for base edesc and link tables */ ++ edesc = qi_cache_zalloc(GFP_DMA | flags); ++ if (!edesc) { ++ dma_unmap_sg(ctx->dev, req->src, src_nents, ++ DMA_TO_DEVICE); ++ return -ENOMEM; ++ } ++ ++ edesc->src_nents = src_nents; ++ sg_table = &edesc->sgt[0]; ++ ++ memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt)); ++ dpaa2_fl_set_final(in_fle, true); ++ dpaa2_fl_set_len(in_fle, to_hash); ++ ++ if (mapped_nents > 1) { ++ int qm_sg_bytes; ++ ++ sg_to_qm_sg_last(req->src, mapped_nents, sg_table, 0); ++ qm_sg_bytes = mapped_nents * sizeof(*sg_table); ++ edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, ++ qm_sg_bytes, ++ DMA_TO_DEVICE); ++ if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) { ++ dev_err(ctx->dev, "unable to map S/G table\n"); ++ ret = -ENOMEM; ++ goto unmap_ctx; ++ } ++ edesc->qm_sg_bytes = qm_sg_bytes; ++ dpaa2_fl_set_format(in_fle, dpaa2_fl_sg); ++ dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma); ++ } else { ++ dpaa2_fl_set_format(in_fle, dpaa2_fl_single); ++ dpaa2_fl_set_addr(in_fle, sg_dma_address(req->src)); ++ } ++ ++ if (*next_buflen) ++ scatterwalk_map_and_copy(next_buf, req->src, to_hash, ++ *next_buflen, 0); ++ ++ state->ctx_dma = dma_map_single(ctx->dev, state->caam_ctx, ++ ctx->ctx_len, DMA_FROM_DEVICE); ++ if (dma_mapping_error(ctx->dev, state->ctx_dma)) { ++ dev_err(ctx->dev, "unable to map ctx\n"); ++ state->ctx_dma = 0; ++ ret = -ENOMEM; ++ goto unmap_ctx; ++ } ++ ++ dpaa2_fl_set_format(out_fle, dpaa2_fl_single); ++ dpaa2_fl_set_addr(out_fle, state->ctx_dma); ++ dpaa2_fl_set_len(out_fle, ctx->ctx_len); ++ ++ req_ctx->flc = &ctx->flc[UPDATE_FIRST]; ++ req_ctx->flc_dma = ctx->flc_dma[UPDATE_FIRST]; ++ req_ctx->cbk = ahash_done_ctx_dst; ++ req_ctx->ctx = &req->base; ++ req_ctx->edesc = edesc; ++ ++ ret = dpaa2_caam_enqueue(ctx->dev, req_ctx); ++ if (ret != -EINPROGRESS && ++ !(ret == -EBUSY && req->base.flags & ++ CRYPTO_TFM_REQ_MAY_BACKLOG)) ++ goto unmap_ctx; ++ ++ state->update = ahash_update_ctx; ++ state->finup = ahash_finup_ctx; ++ state->final = ahash_final_ctx; ++ } else if (*next_buflen) { ++ state->update = ahash_update_no_ctx; ++ state->finup = ahash_finup_no_ctx; ++ state->final = ahash_final_no_ctx; ++ scatterwalk_map_and_copy(next_buf, req->src, 0, ++ req->nbytes, 0); ++ switch_buf(state); ++ } ++#ifdef DEBUG ++ print_hex_dump(KERN_ERR, "next buf@" __stringify(__LINE__)": ", ++ DUMP_PREFIX_ADDRESS, 16, 4, next_buf, *next_buflen, 1); ++#endif ++ ++ return ret; ++unmap_ctx: ++ ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE); ++ qi_cache_free(edesc); ++ return ret; ++} ++ ++static int ahash_finup_first(struct ahash_request *req) ++{ ++ return ahash_digest(req); ++} ++ ++static int ahash_init(struct ahash_request *req) ++{ ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ ++ state->update = ahash_update_first; ++ state->finup = ahash_finup_first; ++ state->final = ahash_final_no_ctx; ++ ++ state->ctx_dma = 0; ++ state->current_buf = 0; ++ state->buf_dma = 0; ++ state->buflen_0 = 0; ++ state->buflen_1 = 0; ++ ++ return 0; ++} ++ ++static int ahash_update(struct ahash_request *req) ++{ ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ ++ return state->update(req); ++} ++ ++static int ahash_finup(struct ahash_request *req) ++{ ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ ++ return state->finup(req); ++} ++ ++static int ahash_final(struct ahash_request *req) ++{ ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ ++ return state->final(req); ++} ++ ++static int ahash_export(struct ahash_request *req, void *out) ++{ ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ struct caam_export_state *export = out; ++ int len; ++ u8 *buf; ++ ++ if (state->current_buf) { ++ buf = state->buf_1; ++ len = state->buflen_1; ++ } else { ++ buf = state->buf_0; ++ len = state->buflen_0; ++ } ++ ++ memcpy(export->buf, buf, len); ++ memcpy(export->caam_ctx, state->caam_ctx, sizeof(export->caam_ctx)); ++ export->buflen = len; ++ export->update = state->update; ++ export->final = state->final; ++ export->finup = state->finup; ++ ++ return 0; ++} ++ ++static int ahash_import(struct ahash_request *req, const void *in) ++{ ++ struct caam_hash_state *state = ahash_request_ctx(req); ++ const struct caam_export_state *export = in; ++ ++ memset(state, 0, sizeof(*state)); ++ memcpy(state->buf_0, export->buf, export->buflen); ++ memcpy(state->caam_ctx, export->caam_ctx, sizeof(state->caam_ctx)); ++ state->buflen_0 = export->buflen; ++ state->update = export->update; ++ state->final = export->final; ++ state->finup = export->finup; ++ ++ return 0; ++} ++ ++struct caam_hash_template { ++ char name[CRYPTO_MAX_ALG_NAME]; ++ char driver_name[CRYPTO_MAX_ALG_NAME]; ++ char hmac_name[CRYPTO_MAX_ALG_NAME]; ++ char hmac_driver_name[CRYPTO_MAX_ALG_NAME]; ++ unsigned int blocksize; ++ struct ahash_alg template_ahash; ++ u32 alg_type; ++}; ++ ++/* ahash descriptors */ ++static struct caam_hash_template driver_hash[] = { ++ { ++ .name = "sha1", ++ .driver_name = "sha1-caam-qi2", ++ .hmac_name = "hmac(sha1)", ++ .hmac_driver_name = "hmac-sha1-caam-qi2", ++ .blocksize = SHA1_BLOCK_SIZE, ++ .template_ahash = { ++ .init = ahash_init, ++ .update = ahash_update, ++ .final = ahash_final, ++ .finup = ahash_finup, ++ .digest = ahash_digest, ++ .export = ahash_export, ++ .import = ahash_import, ++ .setkey = ahash_setkey, ++ .halg = { ++ .digestsize = SHA1_DIGEST_SIZE, ++ .statesize = sizeof(struct caam_export_state), ++ }, ++ }, ++ .alg_type = OP_ALG_ALGSEL_SHA1, ++ }, { ++ .name = "sha224", ++ .driver_name = "sha224-caam-qi2", ++ .hmac_name = "hmac(sha224)", ++ .hmac_driver_name = "hmac-sha224-caam-qi2", ++ .blocksize = SHA224_BLOCK_SIZE, ++ .template_ahash = { ++ .init = ahash_init, ++ .update = ahash_update, ++ .final = ahash_final, ++ .finup = ahash_finup, ++ .digest = ahash_digest, ++ .export = ahash_export, ++ .import = ahash_import, ++ .setkey = ahash_setkey, ++ .halg = { ++ .digestsize = SHA224_DIGEST_SIZE, ++ .statesize = sizeof(struct caam_export_state), ++ }, ++ }, ++ .alg_type = OP_ALG_ALGSEL_SHA224, ++ }, { ++ .name = "sha256", ++ .driver_name = "sha256-caam-qi2", ++ .hmac_name = "hmac(sha256)", ++ .hmac_driver_name = "hmac-sha256-caam-qi2", ++ .blocksize = SHA256_BLOCK_SIZE, ++ .template_ahash = { ++ .init = ahash_init, ++ .update = ahash_update, ++ .final = ahash_final, ++ .finup = ahash_finup, ++ .digest = ahash_digest, ++ .export = ahash_export, ++ .import = ahash_import, ++ .setkey = ahash_setkey, ++ .halg = { ++ .digestsize = SHA256_DIGEST_SIZE, ++ .statesize = sizeof(struct caam_export_state), ++ }, ++ }, ++ .alg_type = OP_ALG_ALGSEL_SHA256, ++ }, { ++ .name = "sha384", ++ .driver_name = "sha384-caam-qi2", ++ .hmac_name = "hmac(sha384)", ++ .hmac_driver_name = "hmac-sha384-caam-qi2", ++ .blocksize = SHA384_BLOCK_SIZE, ++ .template_ahash = { ++ .init = ahash_init, ++ .update = ahash_update, ++ .final = ahash_final, ++ .finup = ahash_finup, ++ .digest = ahash_digest, ++ .export = ahash_export, ++ .import = ahash_import, ++ .setkey = ahash_setkey, ++ .halg = { ++ .digestsize = SHA384_DIGEST_SIZE, ++ .statesize = sizeof(struct caam_export_state), ++ }, ++ }, ++ .alg_type = OP_ALG_ALGSEL_SHA384, ++ }, { ++ .name = "sha512", ++ .driver_name = "sha512-caam-qi2", ++ .hmac_name = "hmac(sha512)", ++ .hmac_driver_name = "hmac-sha512-caam-qi2", ++ .blocksize = SHA512_BLOCK_SIZE, ++ .template_ahash = { ++ .init = ahash_init, ++ .update = ahash_update, ++ .final = ahash_final, ++ .finup = ahash_finup, ++ .digest = ahash_digest, ++ .export = ahash_export, ++ .import = ahash_import, ++ .setkey = ahash_setkey, ++ .halg = { ++ .digestsize = SHA512_DIGEST_SIZE, ++ .statesize = sizeof(struct caam_export_state), ++ }, ++ }, ++ .alg_type = OP_ALG_ALGSEL_SHA512, ++ }, { ++ .name = "md5", ++ .driver_name = "md5-caam-qi2", ++ .hmac_name = "hmac(md5)", ++ .hmac_driver_name = "hmac-md5-caam-qi2", ++ .blocksize = MD5_BLOCK_WORDS * 4, ++ .template_ahash = { ++ .init = ahash_init, ++ .update = ahash_update, ++ .final = ahash_final, ++ .finup = ahash_finup, ++ .digest = ahash_digest, ++ .export = ahash_export, ++ .import = ahash_import, ++ .setkey = ahash_setkey, ++ .halg = { ++ .digestsize = MD5_DIGEST_SIZE, ++ .statesize = sizeof(struct caam_export_state), ++ }, ++ }, ++ .alg_type = OP_ALG_ALGSEL_MD5, ++ } ++}; ++ ++struct caam_hash_alg { ++ struct list_head entry; ++ struct device *dev; ++ int alg_type; ++ struct ahash_alg ahash_alg; ++}; ++ ++static int caam_hash_cra_init(struct crypto_tfm *tfm) ++{ ++ struct crypto_ahash *ahash = __crypto_ahash_cast(tfm); ++ struct crypto_alg *base = tfm->__crt_alg; ++ struct hash_alg_common *halg = ++ container_of(base, struct hash_alg_common, base); ++ struct ahash_alg *alg = ++ container_of(halg, struct ahash_alg, halg); ++ struct caam_hash_alg *caam_hash = ++ container_of(alg, struct caam_hash_alg, ahash_alg); ++ struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm); ++ /* Sizes for MDHA running digests: MD5, SHA1, 224, 256, 384, 512 */ ++ static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE, ++ HASH_MSG_LEN + SHA1_DIGEST_SIZE, ++ HASH_MSG_LEN + 32, ++ HASH_MSG_LEN + SHA256_DIGEST_SIZE, ++ HASH_MSG_LEN + 64, ++ HASH_MSG_LEN + SHA512_DIGEST_SIZE }; ++ dma_addr_t dma_addr; ++ int i; ++ ++ ctx->dev = caam_hash->dev; ++ ++ dma_addr = dma_map_single_attrs(ctx->dev, ctx->flc, sizeof(ctx->flc), ++ DMA_BIDIRECTIONAL, ++ DMA_ATTR_SKIP_CPU_SYNC); ++ if (dma_mapping_error(ctx->dev, dma_addr)) { ++ dev_err(ctx->dev, "unable to map shared descriptors\n"); ++ return -ENOMEM; ++ } ++ ++ for (i = 0; i < HASH_NUM_OP; i++) ++ ctx->flc_dma[i] = dma_addr + i * sizeof(ctx->flc[i]); ++ ++ /* copy descriptor header template value */ ++ ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam_hash->alg_type; ++ ++ ctx->ctx_len = runninglen[(ctx->adata.algtype & ++ OP_ALG_ALGSEL_SUBMASK) >> ++ OP_ALG_ALGSEL_SHIFT]; ++ ++ crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), ++ sizeof(struct caam_hash_state)); ++ ++ return ahash_set_sh_desc(ahash); ++} ++ ++static void caam_hash_cra_exit(struct crypto_tfm *tfm) ++{ ++ struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm); ++ ++ dma_unmap_single_attrs(ctx->dev, ctx->flc_dma[0], sizeof(ctx->flc), ++ DMA_BIDIRECTIONAL, DMA_ATTR_SKIP_CPU_SYNC); ++} ++ ++static struct caam_hash_alg *caam_hash_alloc(struct device *dev, ++ struct caam_hash_template *template, bool keyed) ++{ ++ struct caam_hash_alg *t_alg; ++ struct ahash_alg *halg; ++ struct crypto_alg *alg; ++ ++ t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL); ++ if (!t_alg) ++ return ERR_PTR(-ENOMEM); ++ ++ t_alg->ahash_alg = template->template_ahash; ++ halg = &t_alg->ahash_alg; ++ alg = &halg->halg.base; ++ ++ if (keyed) { ++ snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", ++ template->hmac_name); ++ snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", ++ template->hmac_driver_name); ++ } else { ++ snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", ++ template->name); ++ snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", ++ template->driver_name); ++ } ++ alg->cra_module = THIS_MODULE; ++ alg->cra_init = caam_hash_cra_init; ++ alg->cra_exit = caam_hash_cra_exit; ++ alg->cra_ctxsize = sizeof(struct caam_hash_ctx); ++ alg->cra_priority = CAAM_CRA_PRIORITY; ++ alg->cra_blocksize = template->blocksize; ++ alg->cra_alignmask = 0; ++ alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_TYPE_AHASH; ++ alg->cra_type = &crypto_ahash_type; ++ ++ t_alg->alg_type = template->alg_type; ++ t_alg->dev = dev; ++ ++ return t_alg; ++} ++ ++static void dpaa2_caam_fqdan_cb(struct dpaa2_io_notification_ctx *nctx) ++{ ++ struct dpaa2_caam_priv_per_cpu *ppriv; ++ ++ ppriv = container_of(nctx, struct dpaa2_caam_priv_per_cpu, nctx); ++ napi_schedule_irqoff(&ppriv->napi); ++} ++ ++static int __cold dpaa2_dpseci_dpio_setup(struct dpaa2_caam_priv *priv) ++{ ++ struct device *dev = priv->dev; + struct dpaa2_io_notification_ctx *nctx; + struct dpaa2_caam_priv_per_cpu *ppriv; + int err, i = 0, cpu; @@ -19312,6 +20889,7 @@ index 00000000..102b0841 +} + +static struct list_head alg_list; ++static struct list_head hash_list; + +static int dpaa2_caam_probe(struct fsl_mc_device *dpseci_dev) +{ @@ -19475,6 +21053,61 @@ index 00000000..102b0841 + if (registered) + dev_info(dev, "algorithms registered in /proc/crypto\n"); + ++ /* register hash algorithms the device supports */ ++ INIT_LIST_HEAD(&hash_list); ++ ++ /* ++ * Skip registration of any hashing algorithms if MD block ++ * is not present. ++ */ ++ if (!priv->sec_attr.md_acc_num) ++ return 0; ++ ++ for (i = 0; i < ARRAY_SIZE(driver_hash); i++) { ++ struct caam_hash_alg *t_alg; ++ struct caam_hash_template *alg = driver_hash + i; ++ ++ /* register hmac version */ ++ t_alg = caam_hash_alloc(dev, alg, true); ++ if (IS_ERR(t_alg)) { ++ err = PTR_ERR(t_alg); ++ dev_warn(dev, "%s hash alg allocation failed: %d\n", ++ alg->driver_name, err); ++ continue; ++ } ++ ++ err = crypto_register_ahash(&t_alg->ahash_alg); ++ if (err) { ++ dev_warn(dev, "%s alg registration failed: %d\n", ++ t_alg->ahash_alg.halg.base.cra_driver_name, ++ err); ++ kfree(t_alg); ++ } else { ++ list_add_tail(&t_alg->entry, &hash_list); ++ } ++ ++ /* register unkeyed version */ ++ t_alg = caam_hash_alloc(dev, alg, false); ++ if (IS_ERR(t_alg)) { ++ err = PTR_ERR(t_alg); ++ dev_warn(dev, "%s alg allocation failed: %d\n", ++ alg->driver_name, err); ++ continue; ++ } ++ ++ err = crypto_register_ahash(&t_alg->ahash_alg); ++ if (err) { ++ dev_warn(dev, "%s alg registration failed: %d\n", ++ t_alg->ahash_alg.halg.base.cra_driver_name, ++ err); ++ kfree(t_alg); ++ } else { ++ list_add_tail(&t_alg->entry, &hash_list); ++ } ++ } ++ if (!list_empty(&hash_list)) ++ dev_info(dev, "hash algorithms registered in /proc/crypto\n"); ++ + return err; + +err_bind: @@ -19519,6 +21152,16 @@ index 00000000..102b0841 + } + } + ++ if (hash_list.next) { ++ struct caam_hash_alg *t_hash_alg, *p; ++ ++ list_for_each_entry_safe(t_hash_alg, p, &hash_list, entry) { ++ crypto_unregister_ahash(&t_hash_alg->ahash_alg); ++ list_del(&t_hash_alg->entry); ++ kfree(t_hash_alg); ++ } ++ } ++ + dpaa2_dpseci_disable(priv); + dpaa2_dpseci_dpio_free(priv); + dpaa2_dpseci_free(priv); @@ -19549,7 +21192,7 @@ index 00000000..102b0841 + } + } + -+ dpaa2_fl_set_flc(&req->fd_flt[1], req->flc->flc_dma); ++ dpaa2_fl_set_flc(&req->fd_flt[1], req->flc_dma); + + req->fd_flt_dma = dma_map_single(dev, req->fd_flt, sizeof(req->fd_flt), + DMA_BIDIRECTIONAL); @@ -19562,7 +21205,7 @@ index 00000000..102b0841 + dpaa2_fd_set_format(&fd, dpaa2_fd_list); + dpaa2_fd_set_addr(&fd, req->fd_flt_dma); + dpaa2_fd_set_len(&fd, req->fd_flt[1].len); -+ dpaa2_fd_set_flc(&fd, req->flc->flc_dma); ++ dpaa2_fd_set_flc(&fd, req->flc_dma); + + /* + * There is no guarantee that preemption is disabled here, @@ -19616,12 +21259,9 @@ index 00000000..102b0841 +MODULE_DESCRIPTION("Freescale DPAA2 CAAM Driver"); + +module_fsl_mc_driver(dpaa2_caam_driver); -diff --git a/drivers/crypto/caam/caamalg_qi2.h b/drivers/crypto/caam/caamalg_qi2.h -new file mode 100644 -index 00000000..2ba179db --- /dev/null +++ b/drivers/crypto/caam/caamalg_qi2.h -@@ -0,0 +1,265 @@ +@@ -0,0 +1,281 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor Inc. + * Copyright 2017 NXP @@ -19837,16 +21477,30 @@ index 00000000..2ba179db + struct dpaa2_sg_entry sgt[0]; +}; + ++/* ++ * ahash_edesc - s/w-extended ahash descriptor ++ * @dst_dma: I/O virtual address of req->result ++ * @qm_sg_dma: I/O virtual address of h/w link table ++ * @src_nents: number of segments in input scatterlist ++ * @qm_sg_bytes: length of dma mapped qm_sg space ++ * @sgt: pointer to h/w link table ++ */ ++struct ahash_edesc { ++ dma_addr_t dst_dma; ++ dma_addr_t qm_sg_dma; ++ int src_nents; ++ int qm_sg_bytes; ++ struct dpaa2_sg_entry sgt[0]; ++}; ++ +/** + * caam_flc - Flow Context (FLC) + * @flc: Flow Context options + * @sh_desc: Shared Descriptor -+ * @flc_dma: DMA address of the Flow Context + */ +struct caam_flc { + u32 flc[16]; + u32 sh_desc[MAX_SDLEN]; -+ dma_addr_t flc_dma; +} ____cacheline_aligned; + +enum optype { @@ -19864,6 +21518,7 @@ index 00000000..2ba179db + * fd_flt[1] - FLE pointing to input buffer + * @fd_flt_dma: DMA address for the frame list table + * @flc: Flow Context ++ * @flc_dma: I/O virtual address of Flow Context + * @op_type: operation type + * @cbk: Callback function to invoke when job is completed + * @ctx: arbit context attached with request by the application @@ -19873,6 +21528,7 @@ index 00000000..2ba179db + struct dpaa2_fl_entry fd_flt[2]; + dma_addr_t fd_flt_dma; + struct caam_flc *flc; ++ dma_addr_t flc_dma; + enum optype op_type; + void (*cbk)(void *ctx, u32 err); + void *ctx; @@ -19887,20 +21543,32 @@ index 00000000..2ba179db +int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req); + +#endif /* _CAAMALG_QI2_H_ */ -diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c -index 631337c2..698580b6 100644 --- a/drivers/crypto/caam/caamhash.c +++ b/drivers/crypto/caam/caamhash.c -@@ -72,7 +72,7 @@ +@@ -62,6 +62,7 @@ + #include "error.h" + #include "sg_sw_sec4.h" + #include "key_gen.h" ++#include "caamhash_desc.h" + + #define CAAM_CRA_PRIORITY 3000 + +@@ -71,14 +72,6 @@ + #define CAAM_MAX_HASH_BLOCK_SIZE SHA512_BLOCK_SIZE #define CAAM_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE - /* length of descriptors text */ +-/* length of descriptors text */ -#define DESC_AHASH_BASE (4 * CAAM_CMD_SZ) -+#define DESC_AHASH_BASE (3 * CAAM_CMD_SZ) - #define DESC_AHASH_UPDATE_LEN (6 * CAAM_CMD_SZ) - #define DESC_AHASH_UPDATE_FIRST_LEN (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ) - #define DESC_AHASH_FINAL_LEN (DESC_AHASH_BASE + 5 * CAAM_CMD_SZ) -@@ -103,20 +103,14 @@ struct caam_hash_ctx { +-#define DESC_AHASH_UPDATE_LEN (6 * CAAM_CMD_SZ) +-#define DESC_AHASH_UPDATE_FIRST_LEN (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ) +-#define DESC_AHASH_FINAL_LEN (DESC_AHASH_BASE + 5 * CAAM_CMD_SZ) +-#define DESC_AHASH_FINUP_LEN (DESC_AHASH_BASE + 5 * CAAM_CMD_SZ) +-#define DESC_AHASH_DIGEST_LEN (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ) +- + #define DESC_HASH_MAX_USED_BYTES (DESC_AHASH_FINAL_LEN + \ + CAAM_MAX_HASH_KEY_SIZE) + #define DESC_HASH_MAX_USED_LEN (DESC_HASH_MAX_USED_BYTES / CAAM_CMD_SZ) +@@ -103,20 +96,14 @@ struct caam_hash_ctx { u32 sh_desc_update_first[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned; u32 sh_desc_fin[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned; u32 sh_desc_digest[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned; @@ -19922,7 +21590,7 @@ index 631337c2..698580b6 100644 }; /* ahash state */ -@@ -143,6 +137,31 @@ struct caam_export_state { +@@ -143,6 +130,31 @@ struct caam_export_state { int (*finup)(struct ahash_request *req); }; @@ -19954,7 +21622,7 @@ index 631337c2..698580b6 100644 /* Common job descriptor seq in/out ptr routines */ /* Map state->caam_ctx, and append seq_out_ptr command that points to it */ -@@ -175,36 +194,27 @@ static inline dma_addr_t map_seq_out_ptr_result(u32 *desc, struct device *jrdev, +@@ -175,40 +187,31 @@ static inline dma_addr_t map_seq_out_ptr return dst_dma; } @@ -20000,15 +21668,19 @@ index 631337c2..698580b6 100644 - buf_dma = buf_map_to_sec4_sg(jrdev, sec4_sg, buf, buflen); - else - buf_dma = 0; -- -- return buf_dma; + dma_to_sec4_sg_one(sec4_sg, state->buf_dma, buflen, 0); -+ + +- return buf_dma; + return 0; } /* Map state->caam_ctx, and add it to link table */ -@@ -224,89 +234,54 @@ static inline int ctx_map_to_sec4_sg(u32 *desc, struct device *jrdev, +-static inline int ctx_map_to_sec4_sg(u32 *desc, struct device *jrdev, ++static inline int ctx_map_to_sec4_sg(struct device *jrdev, + struct caam_hash_state *state, int ctx_len, + struct sec4_sg_entry *sec4_sg, u32 flag) + { +@@ -224,124 +227,22 @@ static inline int ctx_map_to_sec4_sg(u32 return 0; } @@ -20041,105 +21713,75 @@ index 631337c2..698580b6 100644 - append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD); -} - - /* +-/* - * For ahash read data from seqin following state->caam_ctx, - * and write resulting class2 context to seqout, which may be state->caam_ctx - * or req->result -+ * For ahash update, final and finup (import_ctx = true) -+ * import context, read and write to seqout -+ * For ahash firsts and digest (import_ctx = false) -+ * read and write to seqout - */ +- */ -static inline void ahash_append_load_str(u32 *desc, int digestsize) -+static inline void ahash_gen_sh_desc(u32 *desc, u32 state, int digestsize, -+ struct caam_hash_ctx *ctx, bool import_ctx) - { +-{ - /* Calculate remaining bytes to read */ - append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ); - - /* Read remaining bytes */ - append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_LAST2 | - FIFOLD_TYPE_MSG | KEY_VLF); -+ u32 op = ctx->adata.algtype; -+ u32 *skip_key_load; - +- - /* Store class2 context bytes */ - append_seq_store(desc, digestsize, LDST_CLASS_2_CCB | - LDST_SRCDST_BYTE_CONTEXT); -} -+ init_sh_desc(desc, HDR_SHARE_SERIAL); - +- -/* - * For ahash update, final and finup, import context, read and write to seqout - */ -static inline void ahash_ctx_data_to_out(u32 *desc, u32 op, u32 state, - int digestsize, - struct caam_hash_ctx *ctx) --{ -- init_sh_desc_key_ahash(desc, ctx); -+ /* Append key if it has been set; ahash update excluded */ -+ if ((state != OP_ALG_AS_UPDATE) && (ctx->adata.keylen)) { -+ /* Skip key loading if already shared */ -+ skip_key_load = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | -+ JUMP_COND_SHRD); - +-{ +- init_sh_desc_key_ahash(desc, ctx); +- - /* Import context from software */ - append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT | - LDST_CLASS_2_CCB | ctx->ctx_len); -+ append_key_as_imm(desc, ctx->key, ctx->adata.keylen_pad, -+ ctx->adata.keylen, CLASS_2 | -+ KEY_DEST_MDHA_SPLIT | KEY_ENC); - +- - /* Class 2 operation */ - append_operation(desc, op | state | OP_ALG_ENCRYPT); -+ set_jump_tgt_here(desc, skip_key_load); - +- - /* - * Load from buf and/or src and write to req->result or state->context - */ - ahash_append_load_str(desc, digestsize); -} -+ op |= OP_ALG_AAI_HMAC_PRECOMP; -+ } - +- -/* For ahash firsts and digest, read and write to seqout */ -static inline void ahash_data_to_out(u32 *desc, u32 op, u32 state, - int digestsize, struct caam_hash_ctx *ctx) -{ - init_sh_desc_key_ahash(desc, ctx); -+ /* If needed, import context from software */ -+ if (import_ctx) -+ append_seq_load(desc, ctx->ctx_len, LDST_CLASS_2_CCB | -+ LDST_SRCDST_BYTE_CONTEXT); - - /* Class 2 operation */ - append_operation(desc, op | state | OP_ALG_ENCRYPT); - - /* - * Load from buf and/or src and write to req->result or state->context -+ * Calculate remaining bytes to read - */ +- +- /* Class 2 operation */ +- append_operation(desc, op | state | OP_ALG_ENCRYPT); +- +- /* +- * Load from buf and/or src and write to req->result or state->context +- */ - ahash_append_load_str(desc, digestsize); -+ append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ); -+ /* Read remaining bytes */ -+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_LAST2 | -+ FIFOLD_TYPE_MSG | KEY_VLF); -+ /* Store class2 context bytes */ -+ append_seq_store(desc, digestsize, LDST_CLASS_2_CCB | -+ LDST_SRCDST_BYTE_CONTEXT); - } - +-} +- static int ahash_set_sh_desc(struct crypto_ahash *ahash) -@@ -314,34 +289,13 @@ static int ahash_set_sh_desc(struct crypto_ahash *ahash) + { struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); int digestsize = crypto_ahash_digestsize(ahash); struct device *jrdev = ctx->jrdev; - u32 have_key = 0; ++ struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent); u32 *desc; - if (ctx->split_key_len) - have_key = OP_ALG_AAI_HMAC_PRECOMP; -- ++ ctx->adata.key_virt = ctx->key; + /* ahash_update shared descriptor */ desc = ctx->sh_desc_update; - @@ -20162,13 +21804,14 @@ index 631337c2..698580b6 100644 - dev_err(jrdev, "unable to map shared descriptor\n"); - return -ENOMEM; - } -+ ahash_gen_sh_desc(desc, OP_ALG_AS_UPDATE, ctx->ctx_len, ctx, true); ++ cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_UPDATE, ctx->ctx_len, ++ ctx->ctx_len, true, ctrlpriv->era); + dma_sync_single_for_device(jrdev, ctx->sh_desc_update_dma, + desc_bytes(desc), DMA_TO_DEVICE); #ifdef DEBUG print_hex_dump(KERN_ERR, "ahash update shdesc@"__stringify(__LINE__)": ", -@@ -350,17 +304,9 @@ static int ahash_set_sh_desc(struct crypto_ahash *ahash) +@@ -350,17 +251,10 @@ static int ahash_set_sh_desc(struct cryp /* ahash_update_first shared descriptor */ desc = ctx->sh_desc_update_first; @@ -20183,13 +21826,14 @@ index 631337c2..698580b6 100644 - dev_err(jrdev, "unable to map shared descriptor\n"); - return -ENOMEM; - } -+ ahash_gen_sh_desc(desc, OP_ALG_AS_INIT, ctx->ctx_len, ctx, false); ++ cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INIT, ctx->ctx_len, ++ ctx->ctx_len, false, ctrlpriv->era); + dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma, + desc_bytes(desc), DMA_TO_DEVICE); #ifdef DEBUG print_hex_dump(KERN_ERR, "ahash update first shdesc@"__stringify(__LINE__)": ", -@@ -369,53 +315,20 @@ static int ahash_set_sh_desc(struct crypto_ahash *ahash) +@@ -369,53 +263,22 @@ static int ahash_set_sh_desc(struct cryp /* ahash_final shared descriptor */ desc = ctx->sh_desc_fin; @@ -20203,7 +21847,8 @@ index 631337c2..698580b6 100644 - dev_err(jrdev, "unable to map shared descriptor\n"); - return -ENOMEM; - } -+ ahash_gen_sh_desc(desc, OP_ALG_AS_FINALIZE, digestsize, ctx, true); ++ cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_FINALIZE, digestsize, ++ ctx->ctx_len, true, ctrlpriv->era); + dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma, + desc_bytes(desc), DMA_TO_DEVICE); #ifdef DEBUG @@ -20243,13 +21888,14 @@ index 631337c2..698580b6 100644 - dev_err(jrdev, "unable to map shared descriptor\n"); - return -ENOMEM; - } -+ ahash_gen_sh_desc(desc, OP_ALG_AS_INITFINAL, digestsize, ctx, false); ++ cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INITFINAL, digestsize, ++ ctx->ctx_len, false, ctrlpriv->era); + dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma, + desc_bytes(desc), DMA_TO_DEVICE); #ifdef DEBUG print_hex_dump(KERN_ERR, "ahash digest shdesc@"__stringify(__LINE__)": ", -@@ -426,14 +339,6 @@ static int ahash_set_sh_desc(struct crypto_ahash *ahash) +@@ -426,14 +289,6 @@ static int ahash_set_sh_desc(struct cryp return 0; } @@ -20264,7 +21910,7 @@ index 631337c2..698580b6 100644 /* Digest hash size if it is too large */ static int hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in, u32 *keylen, u8 *key_out, u32 digestsize) -@@ -469,7 +374,7 @@ static int hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in, +@@ -469,7 +324,7 @@ static int hash_digest_key(struct caam_h } /* Job descriptor to perform unkeyed hash on key_in */ @@ -20273,7 +21919,7 @@ index 631337c2..698580b6 100644 OP_ALG_AS_INITFINAL); append_seq_in_ptr(desc, src_dma, *keylen, 0); append_seq_fifo_load(desc, *keylen, FIFOLD_CLASS_CLASS2 | -@@ -513,10 +418,7 @@ static int hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in, +@@ -513,12 +368,10 @@ static int hash_digest_key(struct caam_h static int ahash_setkey(struct crypto_ahash *ahash, const u8 *key, unsigned int keylen) { @@ -20283,8 +21929,11 @@ index 631337c2..698580b6 100644 - struct device *jrdev = ctx->jrdev; int blocksize = crypto_tfm_alg_blocksize(&ahash->base); int digestsize = crypto_ahash_digestsize(ahash); ++ struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent); int ret; -@@ -539,43 +441,19 @@ static int ahash_setkey(struct crypto_ahash *ahash, + u8 *hashed_key = NULL; + +@@ -539,43 +392,29 @@ static int ahash_setkey(struct crypto_ah key = hashed_key; } @@ -20299,12 +21948,21 @@ index 631337c2..698580b6 100644 - print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); -#endif -- ++ /* ++ * If DKP is supported, use it in the shared descriptor to generate ++ * the split key. ++ */ ++ if (ctrlpriv->era >= 6) { ++ ctx->adata.key_inline = true; ++ ctx->adata.keylen = keylen; ++ ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype & ++ OP_ALG_ALGSEL_MASK); + - ret = gen_split_hash_key(ctx, key, keylen); -+ ret = gen_split_key(ctx->jrdev, ctx->key, &ctx->adata, key, keylen, -+ CAAM_MAX_HASH_KEY_SIZE); - if (ret) - goto bad_free_key; +- if (ret) +- goto bad_free_key; ++ if (ctx->adata.keylen_pad > CAAM_MAX_HASH_KEY_SIZE) ++ goto bad_free_key; - ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len, - DMA_TO_DEVICE); @@ -20312,13 +21970,18 @@ index 631337c2..698580b6 100644 - dev_err(jrdev, "unable to map key i/o memory\n"); - ret = -ENOMEM; - goto error_free_key; -- } - #ifdef DEBUG - print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, ++ memcpy(ctx->key, key, keylen); ++ } else { ++ ret = gen_split_key(ctx->jrdev, ctx->key, &ctx->adata, key, ++ keylen, CAAM_MAX_HASH_KEY_SIZE); ++ if (ret) ++ goto bad_free_key; + } +-#ifdef DEBUG +- print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ", +- DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, - ctx->split_key_pad_len, 1); -+ ctx->adata.keylen_pad, 1); - #endif +-#endif - ret = ahash_set_sh_desc(ahash); - if (ret) { @@ -20332,7 +21995,7 @@ index 631337c2..698580b6 100644 bad_free_key: kfree(hashed_key); crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN); -@@ -604,6 +482,8 @@ static inline void ahash_unmap(struct device *dev, +@@ -604,6 +443,8 @@ static inline void ahash_unmap(struct de struct ahash_edesc *edesc, struct ahash_request *req, int dst_len) { @@ -20341,7 +22004,7 @@ index 631337c2..698580b6 100644 if (edesc->src_nents) dma_unmap_sg(dev, req->src, edesc->src_nents, DMA_TO_DEVICE); if (edesc->dst_dma) -@@ -612,6 +492,12 @@ static inline void ahash_unmap(struct device *dev, +@@ -612,6 +453,12 @@ static inline void ahash_unmap(struct de if (edesc->sec4_sg_bytes) dma_unmap_single(dev, edesc->sec4_sg_dma, edesc->sec4_sg_bytes, DMA_TO_DEVICE); @@ -20354,7 +22017,7 @@ index 631337c2..698580b6 100644 } static inline void ahash_unmap_ctx(struct device *dev, -@@ -643,8 +529,7 @@ static void ahash_done(struct device *jrdev, u32 *desc, u32 err, +@@ -643,8 +490,7 @@ static void ahash_done(struct device *jr dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); #endif @@ -20364,7 +22027,7 @@ index 631337c2..698580b6 100644 if (err) caam_jr_strstatus(jrdev, err); -@@ -671,19 +556,19 @@ static void ahash_done_bi(struct device *jrdev, u32 *desc, u32 err, +@@ -671,19 +517,19 @@ static void ahash_done_bi(struct device struct ahash_edesc *edesc; struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); @@ -20387,7 +22050,7 @@ index 631337c2..698580b6 100644 kfree(edesc); #ifdef DEBUG -@@ -713,8 +598,7 @@ static void ahash_done_ctx_src(struct device *jrdev, u32 *desc, u32 err, +@@ -713,8 +559,7 @@ static void ahash_done_ctx_src(struct de dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); #endif @@ -20397,7 +22060,7 @@ index 631337c2..698580b6 100644 if (err) caam_jr_strstatus(jrdev, err); -@@ -741,19 +625,19 @@ static void ahash_done_ctx_dst(struct device *jrdev, u32 *desc, u32 err, +@@ -741,19 +586,19 @@ static void ahash_done_ctx_dst(struct de struct ahash_edesc *edesc; struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); @@ -20420,7 +22083,7 @@ index 631337c2..698580b6 100644 kfree(edesc); #ifdef DEBUG -@@ -835,13 +719,12 @@ static int ahash_update_ctx(struct ahash_request *req) +@@ -835,13 +680,12 @@ static int ahash_update_ctx(struct ahash struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; @@ -20440,7 +22103,13 @@ index 631337c2..698580b6 100644 int in_len = *buflen + req->nbytes, to_hash; u32 *desc; int src_nents, mapped_nents, sec4_sg_bytes, sec4_sg_src_index; -@@ -895,10 +778,9 @@ static int ahash_update_ctx(struct ahash_request *req) +@@ -890,15 +734,14 @@ static int ahash_update_ctx(struct ahash + edesc->src_nents = src_nents; + edesc->sec4_sg_bytes = sec4_sg_bytes; + +- ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len, ++ ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len, + edesc->sec4_sg, DMA_BIDIRECTIONAL); if (ret) goto unmap_ctx; @@ -20454,7 +22123,7 @@ index 631337c2..698580b6 100644 if (mapped_nents) { sg_to_sec4_sg_last(req->src, mapped_nents, -@@ -909,12 +791,10 @@ static int ahash_update_ctx(struct ahash_request *req) +@@ -909,12 +752,10 @@ static int ahash_update_ctx(struct ahash to_hash - *buflen, *next_buflen, 0); } else { @@ -20469,7 +22138,7 @@ index 631337c2..698580b6 100644 desc = edesc->hw_desc; edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -@@ -969,12 +849,9 @@ static int ahash_final_ctx(struct ahash_request *req) +@@ -969,12 +810,9 @@ static int ahash_final_ctx(struct ahash_ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; @@ -20485,7 +22154,15 @@ index 631337c2..698580b6 100644 u32 *desc; int sec4_sg_bytes, sec4_sg_src_index; int digestsize = crypto_ahash_digestsize(ahash); -@@ -1001,11 +878,11 @@ static int ahash_final_ctx(struct ahash_request *req) +@@ -994,18 +832,17 @@ static int ahash_final_ctx(struct ahash_ + desc = edesc->hw_desc; + + edesc->sec4_sg_bytes = sec4_sg_bytes; +- edesc->src_nents = 0; + +- ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len, ++ ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len, + edesc->sec4_sg, DMA_TO_DEVICE); if (ret) goto unmap_ctx; @@ -20502,7 +22179,7 @@ index 631337c2..698580b6 100644 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, sec4_sg_bytes, DMA_TO_DEVICE); -@@ -1048,12 +925,9 @@ static int ahash_finup_ctx(struct ahash_request *req) +@@ -1048,12 +885,9 @@ static int ahash_finup_ctx(struct ahash_ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; @@ -20518,7 +22195,7 @@ index 631337c2..698580b6 100644 u32 *desc; int sec4_sg_src_index; int src_nents, mapped_nents; -@@ -1082,7 +956,7 @@ static int ahash_finup_ctx(struct ahash_request *req) +@@ -1082,7 +916,7 @@ static int ahash_finup_ctx(struct ahash_ /* allocate space for base edesc and hw desc commands, link tables */ edesc = ahash_edesc_alloc(ctx, sec4_sg_src_index + mapped_nents, @@ -20527,7 +22204,13 @@ index 631337c2..698580b6 100644 flags); if (!edesc) { dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE); -@@ -1098,9 +972,9 @@ static int ahash_finup_ctx(struct ahash_request *req) +@@ -1093,14 +927,14 @@ static int ahash_finup_ctx(struct ahash_ + + edesc->src_nents = src_nents; + +- ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len, ++ ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len, + edesc->sec4_sg, DMA_TO_DEVICE); if (ret) goto unmap_ctx; @@ -20540,7 +22223,7 @@ index 631337c2..698580b6 100644 ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, sec4_sg_src_index, ctx->ctx_len + buflen, -@@ -1136,15 +1010,18 @@ static int ahash_digest(struct ahash_request *req) +@@ -1136,15 +970,18 @@ static int ahash_digest(struct ahash_req { struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); @@ -20561,7 +22244,7 @@ index 631337c2..698580b6 100644 src_nents = sg_nents_for_len(req->src, req->nbytes); if (src_nents < 0) { dev_err(jrdev, "Invalid number of src SG.\n"); -@@ -1215,10 +1092,10 @@ static int ahash_final_no_ctx(struct ahash_request *req) +@@ -1215,10 +1052,10 @@ static int ahash_final_no_ctx(struct aha struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; @@ -20576,7 +22259,15 @@ index 631337c2..698580b6 100644 u32 *desc; int digestsize = crypto_ahash_digestsize(ahash); struct ahash_edesc *edesc; -@@ -1276,13 +1153,12 @@ static int ahash_update_no_ctx(struct ahash_request *req) +@@ -1246,7 +1083,6 @@ static int ahash_final_no_ctx(struct aha + dev_err(jrdev, "unable to map dst\n"); + goto unmap; + } +- edesc->src_nents = 0; + + #ifdef DEBUG + print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ", +@@ -1276,13 +1112,12 @@ static int ahash_update_no_ctx(struct ah struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; @@ -20596,9 +22287,11 @@ index 631337c2..698580b6 100644 int in_len = *buflen + req->nbytes, to_hash; int sec4_sg_bytes, src_nents, mapped_nents; struct ahash_edesc *edesc; -@@ -1331,8 +1207,10 @@ static int ahash_update_no_ctx(struct ahash_request *req) +@@ -1329,10 +1164,11 @@ static int ahash_update_no_ctx(struct ah + + edesc->src_nents = src_nents; edesc->sec4_sg_bytes = sec4_sg_bytes; - edesc->dst_dma = 0; +- edesc->dst_dma = 0; - state->buf_dma = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, - buf, *buflen); @@ -20609,7 +22302,7 @@ index 631337c2..698580b6 100644 sg_to_sec4_sg_last(req->src, mapped_nents, edesc->sec4_sg + 1, 0); -@@ -1342,8 +1220,6 @@ static int ahash_update_no_ctx(struct ahash_request *req) +@@ -1342,8 +1178,6 @@ static int ahash_update_no_ctx(struct ah *next_buflen, 0); } @@ -20618,7 +22311,7 @@ index 631337c2..698580b6 100644 desc = edesc->hw_desc; edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -@@ -1403,12 +1279,9 @@ static int ahash_finup_no_ctx(struct ahash_request *req) +@@ -1403,12 +1237,9 @@ static int ahash_finup_no_ctx(struct aha struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; @@ -20634,7 +22327,7 @@ index 631337c2..698580b6 100644 u32 *desc; int sec4_sg_bytes, sec4_sg_src_index, src_nents, mapped_nents; int digestsize = crypto_ahash_digestsize(ahash); -@@ -1450,9 +1323,9 @@ static int ahash_finup_no_ctx(struct ahash_request *req) +@@ -1450,9 +1281,9 @@ static int ahash_finup_no_ctx(struct aha edesc->src_nents = src_nents; edesc->sec4_sg_bytes = sec4_sg_bytes; @@ -20647,7 +22340,7 @@ index 631337c2..698580b6 100644 ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, 1, buflen, req->nbytes); -@@ -1496,11 +1369,10 @@ static int ahash_update_first(struct ahash_request *req) +@@ -1496,11 +1327,10 @@ static int ahash_update_first(struct aha struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct caam_hash_state *state = ahash_request_ctx(req); struct device *jrdev = ctx->jrdev; @@ -20663,7 +22356,15 @@ index 631337c2..698580b6 100644 int to_hash; u32 *desc; int src_nents, mapped_nents; -@@ -1582,6 +1454,7 @@ static int ahash_update_first(struct ahash_request *req) +@@ -1545,7 +1375,6 @@ static int ahash_update_first(struct aha + } + + edesc->src_nents = src_nents; +- edesc->dst_dma = 0; + + ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, 0, 0, + to_hash); +@@ -1582,6 +1411,7 @@ static int ahash_update_first(struct aha state->final = ahash_final_no_ctx; scatterwalk_map_and_copy(next_buf, req->src, 0, req->nbytes, 0); @@ -20671,7 +22372,7 @@ index 631337c2..698580b6 100644 } #ifdef DEBUG print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ", -@@ -1688,7 +1561,6 @@ struct caam_hash_template { +@@ -1688,7 +1518,6 @@ struct caam_hash_template { unsigned int blocksize; struct ahash_alg template_ahash; u32 alg_type; @@ -20679,7 +22380,7 @@ index 631337c2..698580b6 100644 }; /* ahash descriptors */ -@@ -1714,7 +1586,6 @@ static struct caam_hash_template driver_hash[] = { +@@ -1714,7 +1543,6 @@ static struct caam_hash_template driver_ }, }, .alg_type = OP_ALG_ALGSEL_SHA1, @@ -20687,7 +22388,7 @@ index 631337c2..698580b6 100644 }, { .name = "sha224", .driver_name = "sha224-caam", -@@ -1736,7 +1607,6 @@ static struct caam_hash_template driver_hash[] = { +@@ -1736,7 +1564,6 @@ static struct caam_hash_template driver_ }, }, .alg_type = OP_ALG_ALGSEL_SHA224, @@ -20695,7 +22396,7 @@ index 631337c2..698580b6 100644 }, { .name = "sha256", .driver_name = "sha256-caam", -@@ -1758,7 +1628,6 @@ static struct caam_hash_template driver_hash[] = { +@@ -1758,7 +1585,6 @@ static struct caam_hash_template driver_ }, }, .alg_type = OP_ALG_ALGSEL_SHA256, @@ -20703,7 +22404,7 @@ index 631337c2..698580b6 100644 }, { .name = "sha384", .driver_name = "sha384-caam", -@@ -1780,7 +1649,6 @@ static struct caam_hash_template driver_hash[] = { +@@ -1780,7 +1606,6 @@ static struct caam_hash_template driver_ }, }, .alg_type = OP_ALG_ALGSEL_SHA384, @@ -20711,7 +22412,7 @@ index 631337c2..698580b6 100644 }, { .name = "sha512", .driver_name = "sha512-caam", -@@ -1802,7 +1670,6 @@ static struct caam_hash_template driver_hash[] = { +@@ -1802,7 +1627,6 @@ static struct caam_hash_template driver_ }, }, .alg_type = OP_ALG_ALGSEL_SHA512, @@ -20719,7 +22420,7 @@ index 631337c2..698580b6 100644 }, { .name = "md5", .driver_name = "md5-caam", -@@ -1824,14 +1691,12 @@ static struct caam_hash_template driver_hash[] = { +@@ -1824,14 +1648,12 @@ static struct caam_hash_template driver_ }, }, .alg_type = OP_ALG_ALGSEL_MD5, @@ -20734,7 +22435,7 @@ index 631337c2..698580b6 100644 struct ahash_alg ahash_alg; }; -@@ -1853,6 +1718,7 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm) +@@ -1853,6 +1675,7 @@ static int caam_hash_cra_init(struct cry HASH_MSG_LEN + SHA256_DIGEST_SIZE, HASH_MSG_LEN + 64, HASH_MSG_LEN + SHA512_DIGEST_SIZE }; @@ -20742,7 +22443,7 @@ index 631337c2..698580b6 100644 /* * Get a Job ring from Job Ring driver to ensure in-order -@@ -1863,11 +1729,31 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm) +@@ -1863,11 +1686,31 @@ static int caam_hash_cra_init(struct cry pr_err("Job Ring Device allocation for transform failed\n"); return PTR_ERR(ctx->jrdev); } @@ -20777,7 +22478,7 @@ index 631337c2..698580b6 100644 OP_ALG_ALGSEL_SHIFT]; crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), -@@ -1879,30 +1765,10 @@ static void caam_hash_cra_exit(struct crypto_tfm *tfm) +@@ -1879,30 +1722,10 @@ static void caam_hash_cra_exit(struct cr { struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm); @@ -20812,7 +22513,7 @@ index 631337c2..698580b6 100644 caam_jr_free(ctx->jrdev); } -@@ -1961,7 +1827,6 @@ caam_hash_alloc(struct caam_hash_template *template, +@@ -1961,7 +1784,6 @@ caam_hash_alloc(struct caam_hash_templat alg->cra_type = &crypto_ahash_type; t_alg->alg_type = template->alg_type; @@ -20820,8 +22521,169 @@ index 631337c2..698580b6 100644 return t_alg; } -diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c -index 354a16ab..4fcb378e 100644 +--- /dev/null ++++ b/drivers/crypto/caam/caamhash_desc.c +@@ -0,0 +1,108 @@ ++/* ++ * Shared descriptors for ahash algorithms ++ * ++ * Copyright 2017 NXP ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the names of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") as published by the Free Software ++ * Foundation, either version 2 of that License or (at your option) any ++ * later version. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include "compat.h" ++#include "desc_constr.h" ++#include "caamhash_desc.h" ++ ++/** ++ * cnstr_shdsc_ahash - ahash shared descriptor ++ * @desc: pointer to buffer used for descriptor construction ++ * @adata: pointer to authentication transform definitions. ++ * A split key is required for SEC Era < 6; the size of the split key ++ * is specified in this case. ++ * Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, SHA224, ++ * SHA256, SHA384, SHA512}. ++ * @state: algorithm state OP_ALG_AS_{INIT, FINALIZE, INITFINALIZE, UPDATE} ++ * @digestsize: algorithm's digest size ++ * @ctx_len: size of Context Register ++ * @import_ctx: true if previous Context Register needs to be restored ++ * must be true for ahash update and final ++ * must be false for for ahash first and digest ++ * @era: SEC Era ++ */ ++void cnstr_shdsc_ahash(u32 * const desc, struct alginfo *adata, u32 state, ++ int digestsize, int ctx_len, bool import_ctx, int era) ++{ ++ u32 op = adata->algtype; ++ ++ init_sh_desc(desc, HDR_SHARE_SERIAL); ++ ++ /* Append key if it has been set; ahash update excluded */ ++ if (state != OP_ALG_AS_UPDATE && adata->keylen) { ++ u32 *skip_key_load; ++ ++ /* Skip key loading if already shared */ ++ skip_key_load = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | ++ JUMP_COND_SHRD); ++ ++ if (era < 6) ++ append_key_as_imm(desc, adata->key_virt, ++ adata->keylen_pad, ++ adata->keylen, CLASS_2 | ++ KEY_DEST_MDHA_SPLIT | KEY_ENC); ++ else ++ append_proto_dkp(desc, adata); ++ ++ set_jump_tgt_here(desc, skip_key_load); ++ ++ op |= OP_ALG_AAI_HMAC_PRECOMP; ++ } ++ ++ /* If needed, import context from software */ ++ if (import_ctx) ++ append_seq_load(desc, ctx_len, LDST_CLASS_2_CCB | ++ LDST_SRCDST_BYTE_CONTEXT); ++ ++ /* Class 2 operation */ ++ append_operation(desc, op | state | OP_ALG_ENCRYPT); ++ ++ /* ++ * Load from buf and/or src and write to req->result or state->context ++ * Calculate remaining bytes to read ++ */ ++ append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ); ++ /* Read remaining bytes */ ++ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_LAST2 | ++ FIFOLD_TYPE_MSG | KEY_VLF); ++ /* Store class2 context bytes */ ++ append_seq_store(desc, digestsize, LDST_CLASS_2_CCB | ++ LDST_SRCDST_BYTE_CONTEXT); ++} ++EXPORT_SYMBOL(cnstr_shdsc_ahash); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_DESCRIPTION("FSL CAAM ahash descriptors support"); ++MODULE_AUTHOR("NXP Semiconductors"); +--- /dev/null ++++ b/drivers/crypto/caam/caamhash_desc.h +@@ -0,0 +1,49 @@ ++/* ++ * Shared descriptors for ahash algorithms ++ * ++ * Copyright 2017 NXP ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the names of the above-listed copyright holders nor the ++ * names of any contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") as published by the Free Software ++ * Foundation, either version 2 of that License or (at your option) any ++ * later version. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef _CAAMHASH_DESC_H_ ++#define _CAAMHASH_DESC_H_ ++ ++/* length of descriptors text */ ++#define DESC_AHASH_BASE (3 * CAAM_CMD_SZ) ++#define DESC_AHASH_UPDATE_LEN (6 * CAAM_CMD_SZ) ++#define DESC_AHASH_UPDATE_FIRST_LEN (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ) ++#define DESC_AHASH_FINAL_LEN (DESC_AHASH_BASE + 5 * CAAM_CMD_SZ) ++#define DESC_AHASH_DIGEST_LEN (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ) ++ ++void cnstr_shdsc_ahash(u32 * const desc, struct alginfo *adata, u32 state, ++ int digestsize, int ctx_len, bool import_ctx, int era); ++ ++#endif /* _CAAMHASH_DESC_H_ */ --- a/drivers/crypto/caam/caampkc.c +++ b/drivers/crypto/caam/caampkc.c @@ -18,6 +18,10 @@ @@ -20835,7 +22697,7 @@ index 354a16ab..4fcb378e 100644 static void rsa_io_unmap(struct device *dev, struct rsa_edesc *edesc, struct akcipher_request *req) -@@ -54,6 +58,42 @@ static void rsa_priv_f1_unmap(struct device *dev, struct rsa_edesc *edesc, +@@ -54,6 +58,42 @@ static void rsa_priv_f1_unmap(struct dev dma_unmap_single(dev, pdb->d_dma, key->d_sz, DMA_TO_DEVICE); } @@ -20878,7 +22740,7 @@ index 354a16ab..4fcb378e 100644 /* RSA Job Completion handler */ static void rsa_pub_done(struct device *dev, u32 *desc, u32 err, void *context) { -@@ -90,6 +130,42 @@ static void rsa_priv_f1_done(struct device *dev, u32 *desc, u32 err, +@@ -90,6 +130,42 @@ static void rsa_priv_f1_done(struct devi akcipher_request_complete(req, err); } @@ -20921,7 +22783,7 @@ index 354a16ab..4fcb378e 100644 static struct rsa_edesc *rsa_edesc_alloc(struct akcipher_request *req, size_t desclen) { -@@ -97,8 +173,8 @@ static struct rsa_edesc *rsa_edesc_alloc(struct akcipher_request *req, +@@ -97,8 +173,8 @@ static struct rsa_edesc *rsa_edesc_alloc struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm); struct device *dev = ctx->dev; struct rsa_edesc *edesc; @@ -20932,7 +22794,7 @@ index 354a16ab..4fcb378e 100644 int sgc; int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes; int src_nents, dst_nents; -@@ -258,6 +334,172 @@ static int set_rsa_priv_f1_pdb(struct akcipher_request *req, +@@ -258,6 +334,172 @@ static int set_rsa_priv_f1_pdb(struct ak return 0; } @@ -21105,7 +22967,7 @@ index 354a16ab..4fcb378e 100644 static int caam_rsa_enc(struct akcipher_request *req) { struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req); -@@ -301,24 +543,14 @@ static int caam_rsa_enc(struct akcipher_request *req) +@@ -301,24 +543,14 @@ init_fail: return ret; } @@ -21131,7 +22993,7 @@ index 354a16ab..4fcb378e 100644 /* Allocate extended descriptor */ edesc = rsa_edesc_alloc(req, DESC_RSA_PRIV_F1_LEN); if (IS_ERR(edesc)) -@@ -344,17 +576,147 @@ static int caam_rsa_dec(struct akcipher_request *req) +@@ -344,17 +576,147 @@ init_fail: return ret; } @@ -21285,7 +23147,7 @@ index 354a16ab..4fcb378e 100644 } /** -@@ -370,10 +732,9 @@ static inline u8 *caam_read_raw_data(const u8 *buf, size_t *nbytes) +@@ -370,10 +732,9 @@ static inline u8 *caam_read_raw_data(con { u8 *val; @@ -21299,7 +23161,7 @@ index 354a16ab..4fcb378e 100644 val = kzalloc(*nbytes, GFP_DMA | GFP_KERNEL); if (!val) -@@ -395,7 +756,7 @@ static int caam_rsa_set_pub_key(struct crypto_akcipher *tfm, const void *key, +@@ -395,7 +756,7 @@ static int caam_rsa_set_pub_key(struct c unsigned int keylen) { struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm); @@ -21308,7 +23170,7 @@ index 354a16ab..4fcb378e 100644 struct caam_rsa_key *rsa_key = &ctx->key; int ret; -@@ -437,11 +798,69 @@ static int caam_rsa_set_pub_key(struct crypto_akcipher *tfm, const void *key, +@@ -437,11 +798,69 @@ err: return -ENOMEM; } @@ -21379,7 +23241,7 @@ index 354a16ab..4fcb378e 100644 struct caam_rsa_key *rsa_key = &ctx->key; int ret; -@@ -483,6 +902,8 @@ static int caam_rsa_set_priv_key(struct crypto_akcipher *tfm, const void *key, +@@ -483,6 +902,8 @@ static int caam_rsa_set_priv_key(struct memcpy(rsa_key->d, raw_key.d, raw_key.d_sz); memcpy(rsa_key->e, raw_key.e, raw_key.e_sz); @@ -21388,15 +23250,12 @@ index 354a16ab..4fcb378e 100644 return 0; err: -diff --git a/drivers/crypto/caam/caampkc.h b/drivers/crypto/caam/caampkc.h -index f595d159..87ab75e9 100644 --- a/drivers/crypto/caam/caampkc.h +++ b/drivers/crypto/caam/caampkc.h -@@ -12,22 +12,76 @@ - #include "compat.h" +@@ -13,21 +13,75 @@ #include "pdb.h" -+/** + /** + * caam_priv_key_form - CAAM RSA private key representation + * CAAM RSA private key may have either of three forms. + * @@ -21428,7 +23287,7 @@ index f595d159..87ab75e9 100644 + FORM3 +}; + - /** ++/** * caam_rsa_key - CAAM RSA key structure. Keys are allocated in DMA zone. * @n : RSA modulus raw byte stream * @e : RSA public exponent raw byte stream @@ -21486,8 +23345,6 @@ index f595d159..87ab75e9 100644 +void init_rsa_priv_f3_desc(u32 *desc, struct rsa_priv_f3_pdb *pdb); #endif -diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c -index 9b92af2c..fde07d4f 100644 --- a/drivers/crypto/caam/caamrng.c +++ b/drivers/crypto/caam/caamrng.c @@ -52,7 +52,7 @@ @@ -21499,7 +23356,7 @@ index 9b92af2c..fde07d4f 100644 /* Buffer, its dma address and lock */ struct buf_data { -@@ -100,8 +100,7 @@ static void rng_done(struct device *jrdev, u32 *desc, u32 err, void *context) +@@ -100,8 +100,7 @@ static void rng_done(struct device *jrde { struct buf_data *bd; @@ -21509,7 +23366,7 @@ index 9b92af2c..fde07d4f 100644 if (err) caam_jr_strstatus(jrdev, err); -@@ -196,9 +195,6 @@ static inline int rng_create_sh_desc(struct caam_rng_ctx *ctx) +@@ -196,9 +195,6 @@ static inline int rng_create_sh_desc(str init_sh_desc(desc, HDR_SHARE_SERIAL); @@ -21519,7 +23376,7 @@ index 9b92af2c..fde07d4f 100644 /* Generate random bytes */ append_operation(desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG); -@@ -289,11 +285,7 @@ static int caam_init_rng(struct caam_rng_ctx *ctx, struct device *jrdev) +@@ -289,11 +285,7 @@ static int caam_init_rng(struct caam_rng if (err) return err; @@ -21541,8 +23398,6 @@ index 9b92af2c..fde07d4f 100644 if (!rng_ctx) { err = -ENOMEM; goto free_caam_alloc; -diff --git a/drivers/crypto/caam/compat.h b/drivers/crypto/caam/compat.h -index 7149cd24..4e084f51 100644 --- a/drivers/crypto/caam/compat.h +++ b/drivers/crypto/caam/compat.h @@ -16,6 +16,7 @@ @@ -21553,8 +23408,6 @@ index 7149cd24..4e084f51 100644 #include #include #include -diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c -index 98468b96..8f9642c6 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -2,40 +2,41 @@ @@ -21609,7 +23462,7 @@ index 98468b96..8f9642c6 100644 /* * Descriptor to instantiate RNG State Handle 0 in normal mode and -@@ -270,7 +271,7 @@ static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask) +@@ -274,7 +275,7 @@ static int deinstantiate_rng(struct devi /* * If the corresponding bit is set, then it means the state * handle was initialized by us, and thus it needs to be @@ -21618,7 +23471,7 @@ index 98468b96..8f9642c6 100644 */ if ((1 << sh_idx) & state_handle_mask) { /* -@@ -303,20 +304,24 @@ static int caam_remove(struct platform_device *pdev) +@@ -307,20 +308,24 @@ static int caam_remove(struct platform_d struct device *ctrldev; struct caam_drv_private *ctrlpriv; struct caam_ctrl __iomem *ctrl; @@ -21651,7 +23504,7 @@ index 98468b96..8f9642c6 100644 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); /* Shut down debug views */ -@@ -331,8 +336,8 @@ static int caam_remove(struct platform_device *pdev) +@@ -335,8 +340,8 @@ static int caam_remove(struct platform_d clk_disable_unprepare(ctrlpriv->caam_ipg); clk_disable_unprepare(ctrlpriv->caam_mem); clk_disable_unprepare(ctrlpriv->caam_aclk); @@ -21662,7 +23515,7 @@ index 98468b96..8f9642c6 100644 return 0; } -@@ -366,11 +371,8 @@ static void kick_trng(struct platform_device *pdev, int ent_delay) +@@ -370,11 +375,8 @@ static void kick_trng(struct platform_de */ val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) >> RTSDCTL_ENT_DLY_SHIFT; @@ -21676,7 +23529,7 @@ index 98468b96..8f9642c6 100644 val = rd_reg32(&r4tst->rtsdctl); val = (val & ~RTSDCTL_ENT_DLY_MASK) | -@@ -382,15 +384,12 @@ static void kick_trng(struct platform_device *pdev, int ent_delay) +@@ -386,15 +388,12 @@ static void kick_trng(struct platform_de wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); /* read the control register */ val = rd_reg32(&r4tst->rtmctl); @@ -21695,7 +23548,7 @@ index 98468b96..8f9642c6 100644 } /** -@@ -411,28 +410,26 @@ int caam_get_era(void) +@@ -415,28 +414,26 @@ int caam_get_era(void) } EXPORT_SYMBOL(caam_get_era); @@ -21739,7 +23592,7 @@ index 98468b96..8f9642c6 100644 struct device *dev; struct device_node *nprop, *np; struct caam_ctrl __iomem *ctrl; -@@ -452,9 +449,10 @@ static int caam_probe(struct platform_device *pdev) +@@ -456,9 +453,10 @@ static int caam_probe(struct platform_de dev = &pdev->dev; dev_set_drvdata(dev, ctrlpriv); @@ -21751,7 +23604,7 @@ index 98468b96..8f9642c6 100644 /* Enable clocking */ clk = caam_drv_identify_clk(&pdev->dev, "ipg"); if (IS_ERR(clk)) { -@@ -483,14 +481,16 @@ static int caam_probe(struct platform_device *pdev) +@@ -487,14 +485,16 @@ static int caam_probe(struct platform_de } ctrlpriv->caam_aclk = clk; @@ -21775,7 +23628,7 @@ index 98468b96..8f9642c6 100644 ret = clk_prepare_enable(ctrlpriv->caam_ipg); if (ret < 0) { -@@ -511,11 +511,13 @@ static int caam_probe(struct platform_device *pdev) +@@ -515,11 +515,13 @@ static int caam_probe(struct platform_de goto disable_caam_mem; } @@ -21794,7 +23647,7 @@ index 98468b96..8f9642c6 100644 } /* Get configuration properties from device tree */ -@@ -542,13 +544,13 @@ static int caam_probe(struct platform_device *pdev) +@@ -546,13 +548,13 @@ static int caam_probe(struct platform_de else BLOCK_OFFSET = PG_SIZE_64K; @@ -21813,7 +23666,7 @@ index 98468b96..8f9642c6 100644 BLOCK_OFFSET * DECO_BLOCK_NUMBER ); -@@ -557,12 +559,17 @@ static int caam_probe(struct platform_device *pdev) +@@ -561,12 +563,17 @@ static int caam_probe(struct platform_de /* * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, @@ -21836,7 +23689,7 @@ index 98468b96..8f9642c6 100644 /* * Read the Compile Time paramters and SCFGR to determine -@@ -590,64 +597,67 @@ static int caam_probe(struct platform_device *pdev) +@@ -594,64 +601,69 @@ static int caam_probe(struct platform_de JRSTART_JR1_START | JRSTART_JR2_START | JRSTART_JR3_START); @@ -21852,7 +23705,15 @@ index 98468b96..8f9642c6 100644 - dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); - else - dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); -- ++ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); ++ } else { ++ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); ++ } ++ if (ret) { ++ dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret); ++ goto iounmap_ctrl; ++ } + - /* - * Detect and enable JobRs - * First, find out how many ring spec'ed, allocate references @@ -21863,14 +23724,7 @@ index 98468b96..8f9642c6 100644 - if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || - of_device_is_compatible(np, "fsl,sec4.0-job-ring")) - rspec++; -+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); -+ } else { -+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); -+ } -+ if (ret) { -+ dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret); -+ goto iounmap_ctrl; -+ } ++ ctrlpriv->era = caam_get_era(); - ctrlpriv->jrpdev = devm_kcalloc(&pdev->dev, rspec, - sizeof(*ctrlpriv->jrpdev), GFP_KERNEL); @@ -21943,7 +23797,7 @@ index 98468b96..8f9642c6 100644 } /* If no QI and no rings specified, quit and go home */ -@@ -662,8 +672,10 @@ static int caam_probe(struct platform_device *pdev) +@@ -666,8 +678,10 @@ static int caam_probe(struct platform_de /* * If SEC has RNG version >= 4 and RNG state handle has not been * already instantiated, do RNG instantiation @@ -21955,12 +23809,14 @@ index 98468b96..8f9642c6 100644 ctrlpriv->rng4_sh_init = rd_reg32(&ctrl->r4tst[0].rdsta); /* -@@ -731,77 +743,46 @@ static int caam_probe(struct platform_device *pdev) +@@ -734,78 +748,47 @@ static int caam_probe(struct platform_de + /* Report "alive" for developer to see */ dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, - caam_get_era()); +- caam_get_era()); - dev_info(dev, "job rings = %d, qi = %d\n", - ctrlpriv->total_jobrs, ctrlpriv->qi_present); ++ ctrlpriv->era); + dev_info(dev, "job rings = %d, qi = %d, dpaa2 = %s\n", + ctrlpriv->total_jobrs, ctrlpriv->qi_present, + caam_dpaa2 ? "yes" : "no"); @@ -22067,7 +23923,7 @@ index 98468b96..8f9642c6 100644 ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); ctrlpriv->ctl_kek = debugfs_create_blob("kek", S_IRUSR | -@@ -809,7 +790,7 @@ static int caam_probe(struct platform_device *pdev) +@@ -813,7 +796,7 @@ static int caam_probe(struct platform_de ctrlpriv->ctl, &ctrlpriv->ctl_kek_wrap); @@ -22076,7 +23932,7 @@ index 98468b96..8f9642c6 100644 ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32); ctrlpriv->ctl_tkek = debugfs_create_blob("tkek", S_IRUSR | -@@ -817,7 +798,7 @@ static int caam_probe(struct platform_device *pdev) +@@ -821,7 +804,7 @@ static int caam_probe(struct platform_de ctrlpriv->ctl, &ctrlpriv->ctl_tkek_wrap); @@ -22085,7 +23941,7 @@ index 98468b96..8f9642c6 100644 ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32); ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk", S_IRUSR | -@@ -828,13 +809,17 @@ static int caam_probe(struct platform_device *pdev) +@@ -832,13 +815,17 @@ static int caam_probe(struct platform_de return 0; caam_remove: @@ -22104,7 +23960,7 @@ index 98468b96..8f9642c6 100644 disable_caam_aclk: clk_disable_unprepare(ctrlpriv->caam_aclk); disable_caam_mem: -@@ -844,17 +829,6 @@ static int caam_probe(struct platform_device *pdev) +@@ -848,17 +835,6 @@ disable_caam_ipg: return ret; } @@ -22122,8 +23978,6 @@ index 98468b96..8f9642c6 100644 static struct platform_driver caam_driver = { .driver = { .name = "caam", -diff --git a/drivers/crypto/caam/ctrl.h b/drivers/crypto/caam/ctrl.h -index cac5402a..7e7bf68c 100644 --- a/drivers/crypto/caam/ctrl.h +++ b/drivers/crypto/caam/ctrl.h @@ -10,4 +10,6 @@ @@ -22133,8 +23987,6 @@ index cac5402a..7e7bf68c 100644 +extern bool caam_dpaa2; + #endif /* CTRL_H */ -diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h -index 513b6646..a8c3be73 100644 --- a/drivers/crypto/caam/desc.h +++ b/drivers/crypto/caam/desc.h @@ -22,12 +22,6 @@ @@ -22215,7 +24067,49 @@ index 513b6646..a8c3be73 100644 #define FIFOST_TYPE_SKIP (0x3f << FIFOST_TYPE_SHIFT) /* -@@ -1107,8 +1104,8 @@ struct sec4_sg_entry { +@@ -449,6 +446,18 @@ struct sec4_sg_entry { + #define OP_PCLID_DSAVERIFY (0x16 << OP_PCLID_SHIFT) + #define OP_PCLID_RSAENC_PUBKEY (0x18 << OP_PCLID_SHIFT) + #define OP_PCLID_RSADEC_PRVKEY (0x19 << OP_PCLID_SHIFT) ++#define OP_PCLID_DKP_MD5 (0x20 << OP_PCLID_SHIFT) ++#define OP_PCLID_DKP_SHA1 (0x21 << OP_PCLID_SHIFT) ++#define OP_PCLID_DKP_SHA224 (0x22 << OP_PCLID_SHIFT) ++#define OP_PCLID_DKP_SHA256 (0x23 << OP_PCLID_SHIFT) ++#define OP_PCLID_DKP_SHA384 (0x24 << OP_PCLID_SHIFT) ++#define OP_PCLID_DKP_SHA512 (0x25 << OP_PCLID_SHIFT) ++#define OP_PCLID_DKP_RIF_MD5 (0x60 << OP_PCLID_SHIFT) ++#define OP_PCLID_DKP_RIF_SHA1 (0x61 << OP_PCLID_SHIFT) ++#define OP_PCLID_DKP_RIF_SHA224 (0x62 << OP_PCLID_SHIFT) ++#define OP_PCLID_DKP_RIF_SHA256 (0x63 << OP_PCLID_SHIFT) ++#define OP_PCLID_DKP_RIF_SHA384 (0x64 << OP_PCLID_SHIFT) ++#define OP_PCLID_DKP_RIF_SHA512 (0x65 << OP_PCLID_SHIFT) + + /* Assuming OP_TYPE = OP_TYPE_DECAP_PROTOCOL/ENCAP_PROTOCOL */ + #define OP_PCLID_IPSEC (0x01 << OP_PCLID_SHIFT) +@@ -1098,6 +1107,22 @@ struct sec4_sg_entry { + /* MacSec protinfos */ + #define OP_PCL_MACSEC 0x0001 + ++/* Derived Key Protocol (DKP) Protinfo */ ++#define OP_PCL_DKP_SRC_SHIFT 14 ++#define OP_PCL_DKP_SRC_MASK (3 << OP_PCL_DKP_SRC_SHIFT) ++#define OP_PCL_DKP_SRC_IMM (0 << OP_PCL_DKP_SRC_SHIFT) ++#define OP_PCL_DKP_SRC_SEQ (1 << OP_PCL_DKP_SRC_SHIFT) ++#define OP_PCL_DKP_SRC_PTR (2 << OP_PCL_DKP_SRC_SHIFT) ++#define OP_PCL_DKP_SRC_SGF (3 << OP_PCL_DKP_SRC_SHIFT) ++#define OP_PCL_DKP_DST_SHIFT 12 ++#define OP_PCL_DKP_DST_MASK (3 << OP_PCL_DKP_DST_SHIFT) ++#define OP_PCL_DKP_DST_IMM (0 << OP_PCL_DKP_DST_SHIFT) ++#define OP_PCL_DKP_DST_SEQ (1 << OP_PCL_DKP_DST_SHIFT) ++#define OP_PCL_DKP_DST_PTR (2 << OP_PCL_DKP_DST_SHIFT) ++#define OP_PCL_DKP_DST_SGF (3 << OP_PCL_DKP_DST_SHIFT) ++#define OP_PCL_DKP_KEY_SHIFT 0 ++#define OP_PCL_DKP_KEY_MASK (0xfff << OP_PCL_DKP_KEY_SHIFT) ++ + /* PKI unidirectional protocol protinfo bits */ + #define OP_PCL_PKPROT_TEST 0x0008 + #define OP_PCL_PKPROT_DECRYPT 0x0004 +@@ -1107,8 +1132,8 @@ struct sec4_sg_entry { /* For non-protocol/alg-only op commands */ #define OP_ALG_TYPE_SHIFT 24 #define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT) @@ -22226,7 +24120,7 @@ index 513b6646..a8c3be73 100644 #define OP_ALG_ALGSEL_SHIFT 16 #define OP_ALG_ALGSEL_MASK (0xff << OP_ALG_ALGSEL_SHIFT) -@@ -1249,7 +1246,7 @@ struct sec4_sg_entry { +@@ -1249,7 +1274,7 @@ struct sec4_sg_entry { #define OP_ALG_PKMODE_MOD_PRIMALITY 0x00f /* PKHA mode copy-memory functions */ @@ -22235,7 +24129,7 @@ index 513b6646..a8c3be73 100644 #define OP_ALG_PKMODE_SRC_REG_MASK (7 << OP_ALG_PKMODE_SRC_REG_SHIFT) #define OP_ALG_PKMODE_DST_REG_SHIFT 10 #define OP_ALG_PKMODE_DST_REG_MASK (7 << OP_ALG_PKMODE_DST_REG_SHIFT) -@@ -1445,10 +1442,11 @@ struct sec4_sg_entry { +@@ -1445,10 +1470,11 @@ struct sec4_sg_entry { #define MATH_SRC1_REG2 (0x02 << MATH_SRC1_SHIFT) #define MATH_SRC1_REG3 (0x03 << MATH_SRC1_SHIFT) #define MATH_SRC1_IMM (0x04 << MATH_SRC1_SHIFT) @@ -22248,7 +24142,15 @@ index 513b6646..a8c3be73 100644 /* Destination selectors */ #define MATH_DEST_SHIFT 8 -@@ -1629,4 +1627,31 @@ struct sec4_sg_entry { +@@ -1457,6 +1483,7 @@ struct sec4_sg_entry { + #define MATH_DEST_REG1 (0x01 << MATH_DEST_SHIFT) + #define MATH_DEST_REG2 (0x02 << MATH_DEST_SHIFT) + #define MATH_DEST_REG3 (0x03 << MATH_DEST_SHIFT) ++#define MATH_DEST_DPOVRD (0x07 << MATH_DEST_SHIFT) + #define MATH_DEST_SEQINLEN (0x08 << MATH_DEST_SHIFT) + #define MATH_DEST_SEQOUTLEN (0x09 << MATH_DEST_SHIFT) + #define MATH_DEST_VARSEQINLEN (0x0a << MATH_DEST_SHIFT) +@@ -1629,4 +1656,31 @@ struct sec4_sg_entry { /* Frame Descriptor Command for Replacement Job Descriptor */ #define FD_CMD_REPLACE_JOB_DESC 0x20000000 @@ -22280,8 +24182,6 @@ index 513b6646..a8c3be73 100644 +#define CCTRL_UNLOAD_SBOX 0x10000000 + #endif /* DESC_H */ -diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h -index a8cd8a78..2d9dbeca 100644 --- a/drivers/crypto/caam/desc_constr.h +++ b/drivers/crypto/caam/desc_constr.h @@ -4,6 +4,9 @@ @@ -22341,7 +24241,7 @@ index a8cd8a78..2d9dbeca 100644 { u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ; -@@ -72,19 +76,20 @@ static inline void init_sh_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes) +@@ -72,19 +76,20 @@ static inline void init_sh_desc_pdb(u32 options); } @@ -22365,7 +24265,7 @@ index a8cd8a78..2d9dbeca 100644 { dma_addr_t *offset = (dma_addr_t *)desc_end(desc); -@@ -94,8 +99,8 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr) +@@ -94,8 +99,8 @@ static inline void append_ptr(u32 *desc, CAAM_PTR_SZ / CAAM_CMD_SZ); } @@ -22376,16 +24276,16 @@ index a8cd8a78..2d9dbeca 100644 { PRINT_POS; init_job_desc(desc, HDR_SHARED | options | -@@ -103,7 +108,7 @@ static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len, +@@ -103,7 +108,7 @@ static inline void init_job_desc_shared( append_ptr(desc, ptr); } -static inline void append_data(u32 *desc, void *data, int len) -+static inline void append_data(u32 * const desc, void *data, int len) ++static inline void append_data(u32 * const desc, const void *data, int len) { u32 *offset = desc_end(desc); -@@ -114,7 +119,7 @@ static inline void append_data(u32 *desc, void *data, int len) +@@ -114,7 +119,7 @@ static inline void append_data(u32 *desc (len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ); } @@ -22394,7 +24294,7 @@ index a8cd8a78..2d9dbeca 100644 { u32 *cmd = desc_end(desc); -@@ -125,7 +130,7 @@ static inline void append_cmd(u32 *desc, u32 command) +@@ -125,7 +130,7 @@ static inline void append_cmd(u32 *desc, #define append_u32 append_cmd @@ -22403,7 +24303,7 @@ index a8cd8a78..2d9dbeca 100644 { u32 *offset = desc_end(desc); -@@ -142,14 +147,14 @@ static inline void append_u64(u32 *desc, u64 data) +@@ -142,14 +147,14 @@ static inline void append_u64(u32 *desc, } /* Write command without affecting header, and return pointer to next word */ @@ -22420,7 +24320,7 @@ index a8cd8a78..2d9dbeca 100644 u32 command) { append_cmd(desc, command | len); -@@ -157,7 +162,7 @@ static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len, +@@ -157,7 +162,7 @@ static inline void append_cmd_ptr(u32 *d } /* Write length after pointer, rather than inside command */ @@ -22429,16 +24329,16 @@ index a8cd8a78..2d9dbeca 100644 unsigned int len, u32 command) { append_cmd(desc, command); -@@ -166,7 +171,7 @@ static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr, +@@ -166,7 +171,7 @@ static inline void append_cmd_ptr_extlen append_cmd(desc, len); } -static inline void append_cmd_data(u32 *desc, void *data, int len, -+static inline void append_cmd_data(u32 * const desc, void *data, int len, ++static inline void append_cmd_data(u32 * const desc, const void *data, int len, u32 command) { append_cmd(desc, command | IMMEDIATE | len); -@@ -174,7 +179,7 @@ static inline void append_cmd_data(u32 *desc, void *data, int len, +@@ -174,7 +179,7 @@ static inline void append_cmd_data(u32 * } #define APPEND_CMD_RET(cmd, op) \ @@ -22447,7 +24347,7 @@ index a8cd8a78..2d9dbeca 100644 { \ u32 *cmd = desc_end(desc); \ PRINT_POS; \ -@@ -183,14 +188,15 @@ static inline u32 *append_##cmd(u32 *desc, u32 options) \ +@@ -183,14 +188,15 @@ static inline u32 *append_##cmd(u32 *des } APPEND_CMD_RET(jump, JUMP) APPEND_CMD_RET(move, MOVE) @@ -22465,7 +24365,7 @@ index a8cd8a78..2d9dbeca 100644 { u32 val = caam32_to_cpu(*move_cmd); -@@ -200,7 +206,7 @@ static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd) +@@ -200,7 +206,7 @@ static inline void set_move_tgt_here(u32 } #define APPEND_CMD(cmd, op) \ @@ -22474,7 +24374,7 @@ index a8cd8a78..2d9dbeca 100644 { \ PRINT_POS; \ append_cmd(desc, CMD_##op | options); \ -@@ -208,7 +214,8 @@ static inline void append_##cmd(u32 *desc, u32 options) \ +@@ -208,7 +214,8 @@ static inline void append_##cmd(u32 *des APPEND_CMD(operation, OPERATION) #define APPEND_CMD_LEN(cmd, op) \ @@ -22484,7 +24384,7 @@ index a8cd8a78..2d9dbeca 100644 { \ PRINT_POS; \ append_cmd(desc, CMD_##op | len | options); \ -@@ -220,8 +227,8 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD) +@@ -220,8 +227,8 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_L APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE) #define APPEND_CMD_PTR(cmd, op) \ @@ -22506,7 +24406,7 @@ index a8cd8a78..2d9dbeca 100644 { u32 cmd_src; -@@ -249,7 +256,8 @@ static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len, +@@ -249,7 +256,8 @@ static inline void append_store(u32 *des } #define APPEND_SEQ_PTR_INTLEN(cmd, op) \ @@ -22521,7 +24421,7 @@ index a8cd8a78..2d9dbeca 100644 #define APPEND_CMD_PTR_TO_IMM(cmd, op) \ -static inline void append_##cmd##_as_imm(u32 *desc, void *data, \ -+static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \ ++static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \ unsigned int len, u32 options) \ { \ PRINT_POS; \ @@ -22534,7 +24434,7 @@ index a8cd8a78..2d9dbeca 100644 unsigned int len, u32 options) \ { \ PRINT_POS; \ -@@ -287,7 +295,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR) +@@ -287,7 +295,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_O * the size of its type */ #define APPEND_CMD_PTR_LEN(cmd, op, type) \ @@ -22543,16 +24443,16 @@ index a8cd8a78..2d9dbeca 100644 type len, u32 options) \ { \ PRINT_POS; \ -@@ -304,7 +312,7 @@ APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_PTR, u32) +@@ -304,7 +312,7 @@ APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_ * from length of immediate data provided, e.g., split keys */ #define APPEND_CMD_PTR_TO_IMM2(cmd, op) \ -static inline void append_##cmd##_as_imm(u32 *desc, void *data, \ -+static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \ ++static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \ unsigned int data_len, \ unsigned int len, u32 options) \ { \ -@@ -315,7 +323,7 @@ static inline void append_##cmd##_as_imm(u32 *desc, void *data, \ +@@ -315,7 +323,7 @@ static inline void append_##cmd##_as_imm APPEND_CMD_PTR_TO_IMM2(key, KEY); #define APPEND_CMD_RAW_IMM(cmd, op, type) \ @@ -22561,7 +24461,7 @@ index a8cd8a78..2d9dbeca 100644 u32 options) \ { \ PRINT_POS; \ -@@ -426,3 +434,66 @@ do { \ +@@ -426,3 +434,107 @@ do { \ APPEND_MATH_IMM_u64(LSHIFT, desc, dest, src0, src1, data) #define append_math_rshift_imm_u64(desc, dest, src0, src1, data) \ APPEND_MATH_IMM_u64(RSHIFT, desc, dest, src0, src1, data) @@ -22583,7 +24483,7 @@ index a8cd8a78..2d9dbeca 100644 + unsigned int keylen_pad; + union { + dma_addr_t key_dma; -+ void *key_virt; ++ const void *key_virt; + }; + bool key_inline; +}; @@ -22627,10 +24527,48 @@ index a8cd8a78..2d9dbeca 100644 + return (rem_bytes >= 0) ? 0 : -1; +} + ++/** ++ * append_proto_dkp - Derived Key Protocol (DKP): key -> split key ++ * @desc: pointer to buffer used for descriptor construction ++ * @adata: pointer to authentication transform definitions. ++ * keylen should be the length of initial key, while keylen_pad ++ * the length of the derived (split) key. ++ * Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, SHA224, ++ * SHA256, SHA384, SHA512}. ++ */ ++static inline void append_proto_dkp(u32 * const desc, struct alginfo *adata) ++{ ++ u32 protid; ++ ++ /* ++ * Quick & dirty translation from OP_ALG_ALGSEL_{MD5, SHA*} ++ * to OP_PCLID_DKP_{MD5, SHA*} ++ */ ++ protid = (adata->algtype & OP_ALG_ALGSEL_SUBMASK) | ++ (0x20 << OP_ALG_ALGSEL_SHIFT); ++ ++ if (adata->key_inline) { ++ int words; ++ ++ append_operation(desc, OP_TYPE_UNI_PROTOCOL | protid | ++ OP_PCL_DKP_SRC_IMM | OP_PCL_DKP_DST_IMM | ++ adata->keylen); ++ append_data(desc, adata->key_virt, adata->keylen); ++ ++ /* Reserve space in descriptor buffer for the derived key */ ++ words = (ALIGN(adata->keylen_pad, CAAM_CMD_SZ) - ++ ALIGN(adata->keylen, CAAM_CMD_SZ)) / CAAM_CMD_SZ; ++ if (words) ++ (*desc) = cpu_to_caam32(caam32_to_cpu(*desc) + words); ++ } else { ++ append_operation(desc, OP_TYPE_UNI_PROTOCOL | protid | ++ OP_PCL_DKP_SRC_PTR | OP_PCL_DKP_DST_PTR | ++ adata->keylen); ++ append_ptr(desc, adata->key_dma); ++ } ++} ++ +#endif /* DESC_CONSTR_H */ -diff --git a/drivers/crypto/caam/dpseci.c b/drivers/crypto/caam/dpseci.c -new file mode 100644 -index 00000000..410cd790 --- /dev/null +++ b/drivers/crypto/caam/dpseci.c @@ -0,0 +1,859 @@ @@ -23493,9 +25431,6 @@ index 00000000..410cd790 + + return 0; +} -diff --git a/drivers/crypto/caam/dpseci.h b/drivers/crypto/caam/dpseci.h -new file mode 100644 -index 00000000..d37489c6 --- /dev/null +++ b/drivers/crypto/caam/dpseci.h @@ -0,0 +1,395 @@ @@ -23894,9 +25829,6 @@ index 00000000..d37489c6 + u16 token, struct dpseci_congestion_notification_cfg *cfg); + +#endif /* _DPSECI_H_ */ -diff --git a/drivers/crypto/caam/dpseci_cmd.h b/drivers/crypto/caam/dpseci_cmd.h -new file mode 100644 -index 00000000..7624315e --- /dev/null +++ b/drivers/crypto/caam/dpseci_cmd.h @@ -0,0 +1,261 @@ @@ -24161,8 +26093,6 @@ index 00000000..7624315e +}; + +#endif /* _DPSECI_CMD_H_ */ -diff --git a/drivers/crypto/caam/error.c b/drivers/crypto/caam/error.c -index 33e41ea8..31963397 100644 --- a/drivers/crypto/caam/error.c +++ b/drivers/crypto/caam/error.c @@ -6,11 +6,54 @@ @@ -24277,7 +26207,7 @@ index 33e41ea8..31963397 100644 static const char * const cha_id_list[] = { "", "AES", -@@ -146,10 +237,9 @@ static void report_ccb_status(struct device *jrdev, const u32 status, +@@ -146,10 +237,9 @@ static void report_ccb_status(struct dev strlen(rng_err_id_list[err_id])) { /* RNG-only error */ err_str = rng_err_id_list[err_id]; @@ -24290,7 +26220,7 @@ index 33e41ea8..31963397 100644 /* * CCB ICV check failures are part of normal operation life; -@@ -198,6 +288,27 @@ static void report_deco_status(struct device *jrdev, const u32 status, +@@ -198,6 +288,27 @@ static void report_deco_status(struct de status, error, idx_str, idx, err_str, err_err_code); } @@ -24318,7 +26248,7 @@ index 33e41ea8..31963397 100644 static void report_jr_status(struct device *jrdev, const u32 status, const char *error) { -@@ -212,7 +323,7 @@ static void report_cond_code_status(struct device *jrdev, const u32 status, +@@ -212,7 +323,7 @@ static void report_cond_code_status(stru status, error, __func__); } @@ -24327,7 +26257,7 @@ index 33e41ea8..31963397 100644 { static const struct stat_src { void (*report_ssed)(struct device *jrdev, const u32 status, -@@ -224,7 +335,7 @@ void caam_jr_strstatus(struct device *jrdev, u32 status) +@@ -224,7 +335,7 @@ void caam_jr_strstatus(struct device *jr { report_ccb_status, "CCB" }, { report_jump_status, "Jump" }, { report_deco_status, "DECO" }, @@ -24336,14 +26266,12 @@ index 33e41ea8..31963397 100644 { report_jr_status, "Job Ring" }, { report_cond_code_status, "Condition Code" }, { NULL, NULL }, -@@ -250,4 +361,4 @@ void caam_jr_strstatus(struct device *jrdev, u32 status) +@@ -250,4 +361,4 @@ void caam_jr_strstatus(struct device *jr else dev_err(jrdev, "%d: unknown error source\n", ssrc); } -EXPORT_SYMBOL(caam_jr_strstatus); +EXPORT_SYMBOL(caam_strstatus); -diff --git a/drivers/crypto/caam/error.h b/drivers/crypto/caam/error.h -index b6350b0d..751ddcac 100644 --- a/drivers/crypto/caam/error.h +++ b/drivers/crypto/caam/error.h @@ -7,5 +7,13 @@ @@ -24361,19 +26289,9 @@ index b6350b0d..751ddcac 100644 + int rowsize, int groupsize, struct scatterlist *sg, + size_t tlen, bool ascii); #endif /* CAAM_ERROR_H */ -diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h -index 5d4c0507..a5236125 100644 --- a/drivers/crypto/caam/intern.h +++ b/drivers/crypto/caam/intern.h -@@ -41,6 +41,7 @@ struct caam_drv_private_jr { - struct device *dev; - int ridx; - struct caam_job_ring __iomem *rregs; /* JobR's register space */ -+ struct tasklet_struct irqtask; - int irq; /* One per queue */ - - /* Number of scatterlist crypt transforms active on the JobR */ -@@ -63,10 +64,9 @@ struct caam_drv_private_jr { +@@ -64,10 +64,9 @@ struct caam_drv_private_jr { * Driver-private storage for a single CAAM block instance */ struct caam_drv_private { @@ -24387,7 +26305,15 @@ index 5d4c0507..a5236125 100644 /* Physical-presence section */ struct caam_ctrl __iomem *ctrl; /* controller region */ -@@ -102,11 +102,6 @@ struct caam_drv_private { +@@ -84,6 +83,7 @@ struct caam_drv_private { + u8 qi_present; /* Nonzero if QI present in device */ + int secvio_irq; /* Security violation interrupt number */ + int virt_en; /* Virtualization enabled in CAAM */ ++ int era; /* CAAM Era (internal HW revision) */ + + #define RNG4_MAX_HANDLES 2 + /* RNG4 block */ +@@ -103,11 +103,6 @@ struct caam_drv_private { #ifdef CONFIG_DEBUG_FS struct dentry *dfs_root; struct dentry *ctl; /* controller dir */ @@ -24399,7 +26325,7 @@ index 5d4c0507..a5236125 100644 struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap; struct dentry *ctl_kek, *ctl_tkek, *ctl_tdsk; #endif -@@ -114,4 +109,22 @@ struct caam_drv_private { +@@ -115,4 +110,22 @@ struct caam_drv_private { void caam_jr_algapi_init(struct device *dev); void caam_jr_algapi_remove(struct device *dev); @@ -24422,8 +26348,6 @@ index 5d4c0507..a5236125 100644 +#endif + #endif /* INTERN_H */ -diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c -index 757c27f9..00e87094 100644 --- a/drivers/crypto/caam/jr.c +++ b/drivers/crypto/caam/jr.c @@ -9,6 +9,7 @@ @@ -24449,16 +26373,7 @@ index 757c27f9..00e87094 100644 static int caam_reset_hw_jr(struct device *dev) { struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); -@@ -73,6 +82,8 @@ static int caam_jr_shutdown(struct device *dev) - - ret = caam_reset_hw_jr(dev); - -+ tasklet_kill(&jrp->irqtask); -+ - /* Release interrupt */ - free_irq(jrp->irq, dev); - -@@ -116,6 +127,8 @@ static int caam_jr_remove(struct platform_device *pdev) +@@ -118,6 +127,8 @@ static int caam_jr_remove(struct platfor dev_err(jrdev, "Failed to shut down job ring\n"); irq_dispose_mapping(jrpriv->irq); @@ -24467,51 +26382,10 @@ index 757c27f9..00e87094 100644 return ret; } -@@ -128,7 +141,7 @@ static irqreturn_t caam_jr_interrupt(int irq, void *st_dev) - - /* - * Check the output ring for ready responses, kick -- * the threaded irq if jobs done. -+ * tasklet if jobs done. - */ - irqstate = rd_reg32(&jrp->rregs->jrintstatus); - if (!irqstate) -@@ -150,13 +163,18 @@ static irqreturn_t caam_jr_interrupt(int irq, void *st_dev) - /* Have valid interrupt at this point, just ACK and trigger */ - wr_reg32(&jrp->rregs->jrintstatus, irqstate); - -- return IRQ_WAKE_THREAD; -+ preempt_disable(); -+ tasklet_schedule(&jrp->irqtask); -+ preempt_enable(); -+ -+ return IRQ_HANDLED; - } - --static irqreturn_t caam_jr_threadirq(int irq, void *st_dev) -+/* Deferred service handler, run as interrupt-fired tasklet */ -+static void caam_jr_dequeue(unsigned long devarg) - { - int hw_idx, sw_idx, i, head, tail; -- struct device *dev = st_dev; -+ struct device *dev = (struct device *)devarg; - struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); - void (*usercall)(struct device *dev, u32 *desc, u32 status, void *arg); - u32 *userdesc, userstatus; -@@ -230,8 +248,6 @@ static irqreturn_t caam_jr_threadirq(int irq, void *st_dev) - - /* reenable / unmask IRQs */ - clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0); -- -- return IRQ_HANDLED; - } - - /** -@@ -274,6 +290,36 @@ struct device *caam_jr_alloc(void) - } +@@ -280,6 +291,36 @@ struct device *caam_jr_alloc(void) EXPORT_SYMBOL(caam_jr_alloc); -+/** + /** + * caam_jridx_alloc() - Alloc a specific job ring based on its index. + * + * returns : pointer to the newly allocated physical @@ -24541,33 +26415,11 @@ index 757c27f9..00e87094 100644 +} +EXPORT_SYMBOL(caam_jridx_alloc); + - /** ++/** * caam_jr_free() - Free the Job Ring * @rdev - points to the dev that identifies the Job ring to -@@ -389,10 +435,11 @@ static int caam_jr_init(struct device *dev) - - jrp = dev_get_drvdata(dev); - -+ tasklet_init(&jrp->irqtask, caam_jr_dequeue, (unsigned long)dev); -+ - /* Connect job ring interrupt handler. */ -- error = request_threaded_irq(jrp->irq, caam_jr_interrupt, -- caam_jr_threadirq, IRQF_SHARED, -- dev_name(dev), dev); -+ error = request_irq(jrp->irq, caam_jr_interrupt, IRQF_SHARED, -+ dev_name(dev), dev); - if (error) { - dev_err(dev, "can't connect JobR %d interrupt (%d)\n", - jrp->ridx, jrp->irq); -@@ -454,6 +501,7 @@ static int caam_jr_init(struct device *dev) - out_free_irq: - free_irq(jrp->irq, dev); - out_kill_deq: -+ tasklet_kill(&jrp->irqtask); - return error; - } - -@@ -489,15 +537,28 @@ static int caam_jr_probe(struct platform_device *pdev) + * be released. +@@ -496,15 +537,28 @@ static int caam_jr_probe(struct platform return -ENOMEM; } @@ -24603,7 +26455,7 @@ index 757c27f9..00e87094 100644 /* Identify the interrupt */ jrpriv->irq = irq_of_parse_and_map(nprop, 0); -@@ -517,10 +578,12 @@ static int caam_jr_probe(struct platform_device *pdev) +@@ -524,10 +578,12 @@ static int caam_jr_probe(struct platform atomic_set(&jrpriv->tfm_count, 0); @@ -24617,8 +26469,6 @@ index 757c27f9..00e87094 100644 { .compatible = "fsl,sec-v4.0-job-ring", }, -diff --git a/drivers/crypto/caam/jr.h b/drivers/crypto/caam/jr.h -index 97113a6d..ee4d31c9 100644 --- a/drivers/crypto/caam/jr.h +++ b/drivers/crypto/caam/jr.h @@ -8,7 +8,9 @@ @@ -24631,11 +26481,9 @@ index 97113a6d..ee4d31c9 100644 void caam_jr_free(struct device *rdev); int caam_jr_enqueue(struct device *dev, u32 *desc, void (*cbk)(struct device *dev, u32 *desc, u32 status, -diff --git a/drivers/crypto/caam/key_gen.c b/drivers/crypto/caam/key_gen.c -index 3ce1d5cd..a523ed77 100644 --- a/drivers/crypto/caam/key_gen.c +++ b/drivers/crypto/caam/key_gen.c -@@ -41,15 +41,29 @@ Split key generation----------------------------------------------- +@@ -41,15 +41,29 @@ Split key generation-------------------- [06] 0x64260028 fifostr: class2 mdsplit-jdk len=40 @0xffe04000 */ @@ -24668,7 +26516,7 @@ index 3ce1d5cd..a523ed77 100644 desc = kmalloc(CAAM_CMD_SZ * 6 + CAAM_PTR_SZ * 2, GFP_KERNEL | GFP_DMA); if (!desc) { dev_err(jrdev, "unable to allocate key input memory\n"); -@@ -63,7 +77,7 @@ int gen_split_key(struct device *jrdev, u8 *key_out, int split_key_len, +@@ -63,7 +77,7 @@ int gen_split_key(struct device *jrdev, goto out_free; } @@ -24677,7 +26525,7 @@ index 3ce1d5cd..a523ed77 100644 DMA_FROM_DEVICE); if (dma_mapping_error(jrdev, dma_addr_out)) { dev_err(jrdev, "unable to map key output memory\n"); -@@ -74,7 +88,9 @@ int gen_split_key(struct device *jrdev, u8 *key_out, int split_key_len, +@@ -74,7 +88,9 @@ int gen_split_key(struct device *jrdev, append_key(desc, dma_addr_in, keylen, CLASS_2 | KEY_DEST_CLASS_REG); /* Sets MDHA up into an HMAC-INIT */ @@ -24688,7 +26536,7 @@ index 3ce1d5cd..a523ed77 100644 /* * do a FIFO_LOAD of zero, this will trigger the internal key expansion -@@ -87,7 +103,7 @@ int gen_split_key(struct device *jrdev, u8 *key_out, int split_key_len, +@@ -87,7 +103,7 @@ int gen_split_key(struct device *jrdev, * FIFO_STORE with the explicit split-key content store * (0x26 output type) */ @@ -24697,7 +26545,7 @@ index 3ce1d5cd..a523ed77 100644 LDST_CLASS_2_CCB | FIFOST_TYPE_SPLIT_KEK); #ifdef DEBUG -@@ -108,11 +124,11 @@ int gen_split_key(struct device *jrdev, u8 *key_out, int split_key_len, +@@ -108,11 +124,11 @@ int gen_split_key(struct device *jrdev, #ifdef DEBUG print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ", DUMP_PREFIX_ADDRESS, 16, 4, key_out, @@ -24711,8 +26559,6 @@ index 3ce1d5cd..a523ed77 100644 DMA_FROM_DEVICE); out_unmap_in: dma_unmap_single(jrdev, dma_addr_in, keylen, DMA_TO_DEVICE); -diff --git a/drivers/crypto/caam/key_gen.h b/drivers/crypto/caam/key_gen.h -index c5588f6d..851a7c86 100644 --- a/drivers/crypto/caam/key_gen.h +++ b/drivers/crypto/caam/key_gen.h @@ -5,6 +5,36 @@ @@ -24762,8 +26608,6 @@ index c5588f6d..851a7c86 100644 +int gen_split_key(struct device *jrdev, u8 *key_out, + struct alginfo * const adata, const u8 *key_in, u32 keylen, + int max_keylen); -diff --git a/drivers/crypto/caam/pdb.h b/drivers/crypto/caam/pdb.h -index aaa00dd1..31e59963 100644 --- a/drivers/crypto/caam/pdb.h +++ b/drivers/crypto/caam/pdb.h @@ -483,6 +483,8 @@ struct dsa_verify_pdb { @@ -24847,11 +26691,9 @@ index aaa00dd1..31e59963 100644 +} __packed; + #endif -diff --git a/drivers/crypto/caam/pkc_desc.c b/drivers/crypto/caam/pkc_desc.c -index 4e4183e6..9e2ce6fe 100644 --- a/drivers/crypto/caam/pkc_desc.c +++ b/drivers/crypto/caam/pkc_desc.c -@@ -34,3 +34,39 @@ void init_rsa_priv_f1_desc(u32 *desc, struct rsa_priv_f1_pdb *pdb) +@@ -34,3 +34,39 @@ void init_rsa_priv_f1_desc(u32 *desc, st append_operation(desc, OP_TYPE_UNI_PROTOCOL | OP_PCLID_RSADEC_PRVKEY | RSA_PRIV_KEY_FRM_1); } @@ -24891,9 +26733,6 @@ index 4e4183e6..9e2ce6fe 100644 + append_operation(desc, OP_TYPE_UNI_PROTOCOL | OP_PCLID_RSADEC_PRVKEY | + RSA_PRIV_KEY_FRM_3); +} -diff --git a/drivers/crypto/caam/qi.c b/drivers/crypto/caam/qi.c -new file mode 100644 -index 00000000..48185d55 --- /dev/null +++ b/drivers/crypto/caam/qi.c @@ -0,0 +1,797 @@ @@ -25008,7 +26847,7 @@ index 00000000..48185d55 + + fd.cmd = 0; + fd.format = qm_fd_compound; -+ fd.cong_weight = req->fd_sgt[1].length; ++ fd.cong_weight = caam32_to_cpu(req->fd_sgt[1].length); + fd.addr = dma_map_single(qidev, req->fd_sgt, sizeof(req->fd_sgt), + DMA_BIDIRECTIONAL); + if (dma_mapping_error(qidev, fd.addr)) { @@ -25694,9 +27533,6 @@ index 00000000..48185d55 + dev_info(qidev, "Linux CAAM Queue I/F driver initialised\n"); + return 0; +} -diff --git a/drivers/crypto/caam/qi.h b/drivers/crypto/caam/qi.h -new file mode 100644 -index 00000000..0c2e68b3 --- /dev/null +++ b/drivers/crypto/caam/qi.h @@ -0,0 +1,204 @@ @@ -25904,8 +27740,6 @@ index 00000000..0c2e68b3 +void qi_cache_free(void *obj); + +#endif /* __QI_H__ */ -diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h -index 84d2f838..74eb8c6c 100644 --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h @@ -2,6 +2,7 @@ @@ -25924,7 +27758,7 @@ index 84d2f838..74eb8c6c 100644 #define caam_to_cpu(len) \ static inline u##len caam##len ## _to_cpu(u##len val) \ -@@ -154,13 +156,10 @@ static inline u64 rd_reg64(void __iomem *reg) +@@ -154,13 +156,10 @@ static inline u64 rd_reg64(void __iomem #else /* CONFIG_64BIT */ static inline void wr_reg64(void __iomem *reg, u64 data) { @@ -25940,7 +27774,7 @@ index 84d2f838..74eb8c6c 100644 wr_reg32((u32 __iomem *)(reg), data >> 32); wr_reg32((u32 __iomem *)(reg) + 1, data); } -@@ -168,41 +167,40 @@ static inline void wr_reg64(void __iomem *reg, u64 data) +@@ -168,41 +167,40 @@ static inline void wr_reg64(void __iomem static inline u64 rd_reg64(void __iomem *reg) { @@ -26024,9 +27858,6 @@ index 84d2f838..74eb8c6c 100644 #define JRSTA_CCBERR_JUMP 0x08000000 #define JRSTA_CCBERR_INDEX_MASK 0xff00 #define JRSTA_CCBERR_INDEX_SHIFT 8 -diff --git a/drivers/crypto/caam/sg_sw_qm.h b/drivers/crypto/caam/sg_sw_qm.h -new file mode 100644 -index 00000000..3b3cabc4 --- /dev/null +++ b/drivers/crypto/caam/sg_sw_qm.h @@ -0,0 +1,126 @@ @@ -26156,9 +27987,6 @@ index 00000000..3b3cabc4 +} + +#endif /* __SG_SW_QM_H */ -diff --git a/drivers/crypto/caam/sg_sw_qm2.h b/drivers/crypto/caam/sg_sw_qm2.h -new file mode 100644 -index 00000000..31b44075 --- /dev/null +++ b/drivers/crypto/caam/sg_sw_qm2.h @@ -0,0 +1,81 @@ @@ -26243,8 +28071,6 @@ index 00000000..31b44075 +} + +#endif /* _SG_SW_QM2_H_ */ -diff --git a/drivers/crypto/caam/sg_sw_sec4.h b/drivers/crypto/caam/sg_sw_sec4.h -index 41cd5a35..936b1b63 100644 --- a/drivers/crypto/caam/sg_sw_sec4.h +++ b/drivers/crypto/caam/sg_sw_sec4.h @@ -5,9 +5,19 @@ @@ -26287,7 +28113,7 @@ index 41cd5a35..936b1b63 100644 #ifdef DEBUG print_hex_dump(KERN_ERR, "sec4_sg_ptr@: ", DUMP_PREFIX_ADDRESS, 16, 4, sec4_sg_ptr, -@@ -43,6 +59,14 @@ sg_to_sec4_sg(struct scatterlist *sg, int sg_count, +@@ -43,6 +59,14 @@ sg_to_sec4_sg(struct scatterlist *sg, in return sec4_sg_ptr - 1; } @@ -26302,7 +28128,7 @@ index 41cd5a35..936b1b63 100644 /* * convert scatterlist to h/w link table format * scatterlist must have been previously dma mapped -@@ -52,31 +76,7 @@ static inline void sg_to_sec4_sg_last(struct scatterlist *sg, int sg_count, +@@ -52,31 +76,7 @@ static inline void sg_to_sec4_sg_last(st u16 offset) { sec4_sg_ptr = sg_to_sec4_sg(sg, sg_count, sec4_sg_ptr, offset); @@ -26336,11 +28162,9 @@ index 41cd5a35..936b1b63 100644 - return sg_nents; -} +#endif /* _SG_SW_SEC4_H_ */ -diff --git a/drivers/net/wireless/rsi/rsi_91x_usb.c b/drivers/net/wireless/rsi/rsi_91x_usb.c -index ef5d394f..cc8deece 100644 --- a/drivers/net/wireless/rsi/rsi_91x_usb.c +++ b/drivers/net/wireless/rsi/rsi_91x_usb.c -@@ -516,7 +516,7 @@ static int rsi_probe(struct usb_interface *pfunction, +@@ -516,7 +516,7 @@ err: /** * rsi_disconnect() - This function performs the reverse of the probe function, @@ -26349,11 +28173,9 @@ index ef5d394f..cc8deece 100644 * @pfunction: Pointer to the USB interface structure. * * Return: None. -diff --git a/drivers/staging/wilc1000/linux_wlan.c b/drivers/staging/wilc1000/linux_wlan.c -index defffa75..ec88ed9c 100644 --- a/drivers/staging/wilc1000/linux_wlan.c +++ b/drivers/staging/wilc1000/linux_wlan.c -@@ -211,7 +211,7 @@ static void deinit_irq(struct net_device *dev) +@@ -211,7 +211,7 @@ static void deinit_irq(struct net_device vif = netdev_priv(dev); wilc = vif->wilc; @@ -26362,11 +28184,9 @@ index defffa75..ec88ed9c 100644 if (wilc->dev_irq_num) { free_irq(wilc->dev_irq_num, wilc); gpio_free(wilc->gpio); -diff --git a/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c b/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c -index 60d8b055..02d3e721 100644 --- a/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c +++ b/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c -@@ -2359,7 +2359,7 @@ int wilc_deinit_host_int(struct net_device *net) +@@ -2359,7 +2359,7 @@ int wilc_deinit_host_int(struct net_devi del_timer_sync(&wilc_during_ip_timer); if (s32Error) @@ -26375,9 +28195,6 @@ index 60d8b055..02d3e721 100644 return s32Error; } -diff --git a/include/crypto/acompress.h b/include/crypto/acompress.h -new file mode 100644 -index 00000000..e328b524 --- /dev/null +++ b/include/crypto/acompress.h @@ -0,0 +1,269 @@ @@ -26650,9 +28467,6 @@ index 00000000..e328b524 +} + +#endif -diff --git a/include/crypto/internal/acompress.h b/include/crypto/internal/acompress.h -new file mode 100644 -index 00000000..1de2b5af --- /dev/null +++ b/include/crypto/internal/acompress.h @@ -0,0 +1,81 @@ @@ -26737,9 +28551,6 @@ index 00000000..1de2b5af +int crypto_unregister_acomp(struct acomp_alg *alg); + +#endif -diff --git a/include/crypto/internal/scompress.h b/include/crypto/internal/scompress.h -new file mode 100644 -index 00000000..3fda3c56 --- /dev/null +++ b/include/crypto/internal/scompress.h @@ -0,0 +1,136 @@ @@ -26879,8 +28690,6 @@ index 00000000..3fda3c56 +int crypto_unregister_scomp(struct scomp_alg *alg); + +#endif -diff --git a/include/linux/crypto.h b/include/linux/crypto.h -index 7cee5551..8348d83d 100644 --- a/include/linux/crypto.h +++ b/include/linux/crypto.h @@ -50,6 +50,8 @@ @@ -26900,8 +28709,6 @@ index 7cee5551..8348d83d 100644 #define CRYPTO_ALG_LARVAL 0x00000010 #define CRYPTO_ALG_DEAD 0x00000020 -diff --git a/include/uapi/linux/cryptouser.h b/include/uapi/linux/cryptouser.h -index 79b5ded2..11d21fce 100644 --- a/include/uapi/linux/cryptouser.h +++ b/include/uapi/linux/cryptouser.h @@ -46,6 +46,7 @@ enum crypto_attr_type_t { @@ -26922,8 +28729,6 @@ index 79b5ded2..11d21fce 100644 + #define CRYPTO_REPORT_MAXSIZE (sizeof(struct crypto_user_alg) + \ sizeof(struct crypto_report_blkcipher)) -diff --git a/scripts/spelling.txt b/scripts/spelling.txt -index 163c720d..8392f89c 100644 --- a/scripts/spelling.txt +++ b/scripts/spelling.txt @@ -305,6 +305,9 @@ defintion||definition @@ -26936,11 +28741,9 @@ index 163c720d..8392f89c 100644 deivce||device delared||declared delare||declare -diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c -index 504c7cd7..d8577374 100644 --- a/sound/soc/amd/acp-pcm-dma.c +++ b/sound/soc/amd/acp-pcm-dma.c -@@ -506,7 +506,7 @@ static int acp_init(void __iomem *acp_mmio) +@@ -506,7 +506,7 @@ static int acp_init(void __iomem *acp_mm return 0; } @@ -26949,6 +28752,3 @@ index 504c7cd7..d8577374 100644 static int acp_deinit(void __iomem *acp_mmio) { u32 val; --- -2.14.1 -