X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=target%2Flinux%2Fipq806x%2Ffiles-4.19%2Farch%2Farm%2Fboot%2Fdts%2Fqcom-ipq8064.dtsi;h=b3ad6db46d424096fefc721b938f7ce62c14862a;hb=1acc054341d1e1163f329b54b28562d9724f12b7;hp=8387460d2714e79ec88eeacc0e1b9122c895938b;hpb=c5d2f3c4765a93dbca9654858a8dec8bf307ad5f;p=oweals%2Fopenwrt.git diff --git a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi index 8387460d27..b3ad6db46d 100644 --- a/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -70,6 +70,7 @@ CPU_SPC: spc { compatible = "qcom,idle-state-spc", "arm,idle-state"; + status = "okay"; entry-latency-us = <400>; exit-latency-us = <900>; min-residency-us = <3000>; @@ -433,7 +434,8 @@ cpu-pmu { compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; + interrupts = ; }; reserved-memory { @@ -533,7 +535,7 @@ clock-names = "ahbix-clk", "mi2s-osr-clk", "mi2s-bit-clk"; - interrupts = <0 85 1>; + interrupts = ; interrupt-names = "lpass-irq-lpaif"; reg = <0x28100000 0x10000>; reg-names = "lpass-lpaif"; @@ -558,9 +560,9 @@ reg = <0x108000 0x1000>; qcom,ipc = <&l2cc 0x8 2>; - interrupts = <0 19 0>, - <0 21 0>, - <0 22 0>; + interrupts = , + , + ; interrupt-names = "ack", "err", "wakeup"; @@ -625,13 +627,13 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 16 0x4>; + interrupts = ; pcie0_pins: pcie0_pinmux { mux { pins = "gpio3"; function = "pcie1_rst"; - drive-strength = <2>; + drive-strength = <12>; bias-disable; }; }; @@ -640,7 +642,7 @@ mux { pins = "gpio48"; function = "pcie2_rst"; - drive-strength = <2>; + drive-strength = <12>; bias-disable; }; }; @@ -649,11 +651,39 @@ mux { pins = "gpio63"; function = "pcie3_rst"; - drive-strength = <2>; + drive-strength = <12>; bias-disable; output-low; }; }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + drive-strength = <10>; + bias-none; + }; + }; + + leds_pins: leds_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", + "gpio26", "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + buttons_pins: buttons_pins { + mux { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; intc: interrupt-controller@2000000 { @@ -665,12 +695,18 @@ }; timer@200a000 { - compatible = "qcom,kpss-timer", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>, - <1 4 0x301>, - <1 5 0x301>; + compatible = "qcom,kpss-timer", + "qcom,kpss-wdt-ipq8064", "qcom,msm-timer"; + interrupts = , + , + , + , + ; reg = <0x0200a000 0x100>; clock-frequency = <25000000>, <32768>; @@ -698,13 +734,13 @@ }; saw0: regulator@2089000 { - compatible = "qcom,saw2", "syscon"; + compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; saw1: regulator@2099000 { - compatible = "qcom,saw2", "syscon"; + compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; @@ -737,7 +773,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x12490000 0x1000>, <0x12480000 0x1000>; - interrupts = <0 195 0x0>; + interrupts = ; clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -746,7 +782,7 @@ i2c@124a0000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x124a0000 0x1000>; - interrupts = <0 196 0>; + interrupts = ; clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; clock-names = "core", "iface"; @@ -775,7 +811,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16340000 0x1000>, <0x16300000 0x1000>; - interrupts = <0 152 0x0>; + interrupts = ; clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -784,7 +820,7 @@ i2c@16380000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x16380000 0x1000>; - interrupts = <0 153 0>; + interrupts = ; clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; clock-names = "core", "iface"; @@ -812,7 +848,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x1a240000 0x1000>, <0x1a200000 0x1000>; - interrupts = <0 154 0x0>; + interrupts = ; clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -821,7 +857,7 @@ i2c@1a280000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x1a280000 0x1000>; - interrupts = <0 155 0>; + interrupts = ; clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; @@ -834,7 +870,7 @@ spi@1a280000 { compatible = "qcom,spi-qup-v1.1.1"; reg = <0x1a280000 0x1000>; - interrupts = <0 155 0>; + interrupts = ; clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; @@ -845,6 +881,29 @@ }; }; + gsbi7: gsbi@16600000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <7>; + reg = <0x16600000 0x100>; + clocks = <&gcc GSBI7_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + syscon-tcsr = <&tcsr>; + + gsbi7_serial: serial@16640000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16640000 0x1000>, + <0x16600000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + sata_phy: sata-phy@1b400000 { compatible = "qcom,ipq806x-sata-phy"; reg = <0x1b400000 0x200>; @@ -856,13 +915,13 @@ status = "disabled"; }; - sata@29000000 { + sata: sata@29000000 { compatible = "qcom,ipq806x-ahci", "generic-ahci"; reg = <0x29000000 0x180>; ports-implemented = <0x1>; - interrupts = <0 209 0x0>; + interrupts = ; clocks = <&gcc SFAB_SATA_S_H_CLK>, <&gcc SATA_H_CLK>, @@ -899,7 +958,7 @@ reg = <0x900000 0x3680>; nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; - interrupts = <0 178 0>; + interrupts = ; #thermal-sensor-cells = <1>; }; @@ -920,64 +979,41 @@ reg = <0x01200600 0x100>; }; - hs_phy_1: phy@100f8800 { - compatible = "qcom,dwc3-hs-usb-phy"; - reg = <0x100f8800 0x30>; - clocks = <&gcc USB30_1_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - status = "disabled"; - }; - - ss_phy_1: phy@100f8830 { - compatible = "qcom,dwc3-ss-usb-phy"; - reg = <0x100f8830 0x30>; - clocks = <&gcc USB30_1_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - status = "disabled"; - }; - - hs_phy_0: phy@110f8800 { + hs_phy_0: hs_phy_0 { compatible = "qcom,dwc3-hs-usb-phy"; - reg = <0x110f8800 0x30>; + regmap = <&usb3_0>; clocks = <&gcc USB30_0_UTMI_CLK>; clock-names = "ref"; #phy-cells = <0>; - - status = "disabled"; }; - ss_phy_0: phy@110f8830 { + ss_phy_0: ss_phy_0 { compatible = "qcom,dwc3-ss-usb-phy"; - reg = <0x110f8830 0x30>; + regmap = <&usb3_0>; clocks = <&gcc USB30_0_MASTER_CLK>; clock-names = "ref"; #phy-cells = <0>; - - status = "disabled"; }; - usb3_0: usb30@0 { - compatible = "qcom,dwc3"; + usb3_0: usb3@110f8800 { + compatible = "qcom,dwc3", "syscon"; #address-cells = <1>; #size-cells = <1>; + reg = <0x110f8800 0x8000>; clocks = <&gcc USB30_0_MASTER_CLK>; clock-names = "core"; ranges; resets = <&gcc USB30_0_MASTER_RESET>; - reset-names = "usb30_0_mstr_rst"; + reset-names = "master"; status = "disabled"; dwc3_0: dwc3@11000000 { compatible = "snps,dwc3"; reg = <0x11000000 0xcd00>; - interrupts = <0 110 0x4>; + interrupts = ; phys = <&hs_phy_0>, <&ss_phy_0>; phy-names = "usb2-phy", "usb3-phy"; dr_mode = "host"; @@ -985,24 +1021,41 @@ }; }; - usb3_1: usb30@1 { - compatible = "qcom,dwc3"; + hs_phy_1: hs_phy_1 { + compatible = "qcom,dwc3-hs-usb-phy"; + regmap = <&usb3_1>; + clocks = <&gcc USB30_1_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + }; + + ss_phy_1: ss_phy_1 { + compatible = "qcom,dwc3-ss-usb-phy"; + regmap = <&usb3_1>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + }; + + usb3_1: usb3@100f8800 { + compatible = "qcom,dwc3", "syscon"; #address-cells = <1>; #size-cells = <1>; + reg = <0x100f8800 0x8000>; clocks = <&gcc USB30_1_MASTER_CLK>; clock-names = "core"; ranges; resets = <&gcc USB30_1_MASTER_RESET>; - reset-names = "usb30_1_mstr_rst"; + reset-names = "master"; status = "disabled"; dwc3_1: dwc3@10000000 { compatible = "snps,dwc3"; reg = <0x10000000 0xcd00>; - interrupts = <0 205 0x4>; + interrupts = ; phys = <&hs_phy_1>, <&ss_phy_1>; phy-names = "usb2-phy", "usb3-phy"; dr_mode = "host"; @@ -1027,7 +1080,7 @@ ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */ 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ - interrupts = ; + interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; @@ -1081,7 +1134,7 @@ ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */ 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ - interrupts = ; + interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; @@ -1135,7 +1188,7 @@ ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */ 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ - interrupts = ; + interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; @@ -1175,7 +1228,7 @@ adm_dma: dma@18300000 { compatible = "qcom,adm"; reg = <0x18300000 0x100000>; - interrupts = <0 170 0>; + interrupts = ; #dma-cells = <1>; clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; @@ -1192,7 +1245,7 @@ status = "disabled"; }; - nand@1ac00000 { + nand: nand@1ac00000 { compatible = "qcom,ipq806x-nand"; reg = <0x1ac00000 0x800>; @@ -1331,7 +1384,7 @@ sdcc1bam:dma@12402000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12402000 0x8000>; - interrupts = <0 98 0>; + interrupts = ; clocks = <&gcc SDC1_H_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; @@ -1341,7 +1394,7 @@ sdcc3bam:dma@12182000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12182000 0x8000>; - interrupts = <0 96 0>; + interrupts = ; clocks = <&gcc SDC3_H_CLK>; clock-names = "bam_clk"; #dma-cells = <1>;