X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=target%2Flinux%2Fbrcm63xx%2Fpatches-3.10%2F411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch;h=f5ef8a35f274e9631c022ae6c3630affb1360bc6;hb=d0ad8c00b6cc0716feae5d12c2ae5b4717c4ac29;hp=516becdece5a9dfb9027142f1b420ba921a3340b;hpb=d9a20b6f461c3be0278ab8e05c2338f7b232482f;p=oweals%2Fopenwrt.git

diff --git a/target/linux/brcm63xx/patches-3.10/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch b/target/linux/brcm63xx/patches-3.10/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch
index 516becdece..f5ef8a35f2 100644
--- a/target/linux/brcm63xx/patches-3.10/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch
+++ b/target/linux/brcm63xx/patches-3.10/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch
@@ -24,9 +24,9 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  #include <bcm63xx_regs.h>
  #include <bcm63xx_io.h>
  
-@@ -55,6 +58,21 @@ static struct platform_device mtd_dev =
- 	},
- };
+@@ -63,6 +66,21 @@ void __init bcm63xx_flash_force_phys_bas
+ 	mtd_resources[0].end = end;
+ }
  
 +static struct flash_platform_data bcm63xx_flash_data = {
 +	.part_probe_types	= bcm63xx_part_types,
@@ -46,8 +46,12 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  static int __init bcm63xx_detect_flash_type(void)
  {
  	u32 val;
-@@ -62,6 +80,11 @@ static int __init bcm63xx_detect_flash_t
+@@ -70,9 +88,15 @@ static int __init bcm63xx_detect_flash_t
  	switch (bcm63xx_get_cpu_id()) {
+ 	case BCM6318_CPU_ID:
+ 		/* only support serial flash */
++		bcm63xx_spi_flash_info[0].max_speed_hz = 62500000;
+ 		return BCM63XX_FLASH_TYPE_SERIAL;
  	case BCM6328_CPU_ID:
  		val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
 +		if (val & STRAPBUS_6328_HSSPI_CLK_FAST)
@@ -58,7 +62,18 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  		if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
  			return BCM63XX_FLASH_TYPE_SERIAL;
  		else
-@@ -86,6 +109,9 @@ static int __init bcm63xx_detect_flash_t
+@@ -91,12 +115,20 @@ static int __init bcm63xx_detect_flash_t
+ 			return BCM63XX_FLASH_TYPE_SERIAL;
+ 	case BCM6362_CPU_ID:
+ 		val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
++		if (val & STRAPBUS_6362_HSSPI_CLK_FAST)
++			bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
++		else
++			bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
++
+ 		if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
+ 			return BCM63XX_FLASH_TYPE_SERIAL;
+ 		else
  			return BCM63XX_FLASH_TYPE_NAND;
  	case BCM6368_CPU_ID:
  		val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
@@ -68,13 +83,26 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  		switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
  		case STRAPBUS_6368_BOOT_SEL_NAND:
  			return BCM63XX_FLASH_TYPE_NAND;
-@@ -117,8 +143,14 @@ int __init bcm63xx_flash_register(void)
+@@ -107,6 +139,11 @@ static int __init bcm63xx_detect_flash_t
+ 		}
+ 	case BCM63268_CPU_ID:
+ 		val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
++		if (val & STRAPBUS_63268_HSSPI_CLK_FAST)
++			bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
++		else
++			bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
++
+ 		if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
+ 			return BCM63XX_FLASH_TYPE_SERIAL;
+ 		else
+@@ -176,8 +213,15 @@ int __init bcm63xx_flash_register(void)
  
  		return platform_device_register(&mtd_dev);
  	case BCM63XX_FLASH_TYPE_SERIAL:
 -		pr_warn("unsupported serial flash detected\n");
 -		return -ENODEV;
-+		if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
++		if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||
++		    BCMCPU_IS_63268())
 +			bcm63xx_spi_flash_info[0].bus_num = 1;
 +
 +		if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
@@ -87,7 +115,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  		return -ENODEV;
 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -672,6 +672,7 @@
+@@ -827,6 +827,7 @@
  #define GPIO_STRAPBUS_REG		0x40
  #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
  #define STRAPBUS_6358_BOOT_SEL_SERIAL	(0 << 1)
@@ -95,8 +123,8 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  #define STRAPBUS_6368_BOOT_SEL_MASK	0x3
  #define STRAPBUS_6368_BOOT_SEL_NAND	0
  #define STRAPBUS_6368_BOOT_SEL_SERIAL	1
-@@ -1513,6 +1514,7 @@
- #define STRAPBUS_6362_BOOT_SEL_NAND	(0 << 15)
+@@ -1697,6 +1698,7 @@
+ #define IDDQ_CTRL_63268_USBH		(1 << 4)
  
  #define MISC_STRAPBUS_6328_REG		0x240
 +#define STRAPBUS_6328_HSSPI_CLK_FAST	(1 << 4)