X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=target%2Flinux%2Fbrcm63xx%2Ffiles%2Farch%2Fmips%2Fbcm63xx%2Fcpu.c;h=937c830b9135077be6ebd2280adcff8da8a4fec6;hb=5138aa203ee761847a56143eb3ab6136df36ae51;hp=2b1a9b46dab95795fa5ea7a856dfab0f54d823cc;hpb=13a8ed9ca0f218e12bad38698a71b5b25e43f168;p=oweals%2Fopenwrt.git

diff --git a/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c b/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
index 2b1a9b46da..937c830b91 100644
--- a/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
+++ b/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
@@ -88,11 +88,27 @@ static const unsigned long bcm96338_regs_spi[] = {
  */
 
 static const unsigned long bcm96345_regs_base[] = {
+	[RSET_DSL_LMEM]		= BCM_6345_DSL_LMEM_BASE,
 	[RSET_PERF]		= BCM_6345_PERF_BASE,
 	[RSET_TIMER]		= BCM_6345_TIMER_BASE,
 	[RSET_WDT]		= BCM_6345_WDT_BASE,
 	[RSET_UART0]		= BCM_6345_UART0_BASE,
 	[RSET_GPIO]		= BCM_6345_GPIO_BASE,
+	[RSET_SPI]		= BCM_6345_SPI_BASE,
+	[RSET_UDC0]		= BCM_6345_UDC0_BASE,
+	[RSET_OHCI0]		= BCM_6345_OHCI0_BASE,
+	[RSET_OHCI_PRIV]	= BCM_6345_OHCI_PRIV_BASE,
+	[RSET_USBH_PRIV]	= BCM_6345_USBH_PRIV_BASE,
+	[RSET_MPI]		= BCM_6345_MPI_BASE,
+	[RSET_PCMCIA]		= BCM_6345_PCMCIA_BASE,
+	[RSET_DSL]		= BCM_6345_DSL_BASE,
+	[RSET_ENET0]		= BCM_6345_ENET0_BASE,
+	[RSET_ENET1]		= BCM_6345_ENET1_BASE,
+	[RSET_ENETDMA]		= BCM_6345_ENETDMA_BASE,
+	[RSET_EHCI0]		= BCM_6345_EHCI0_BASE,
+	[RSET_SDRAM]		= BCM_6345_SDRAM_BASE,
+	[RSET_MEMC]		= BCM_6345_MEMC_BASE,
+	[RSET_DDR]		= BCM_6345_DDR_BASE,
 };
 
 static const int bcm96345_irqs[] = {
@@ -101,6 +117,8 @@ static const int bcm96345_irqs[] = {
 	[IRQ_DSL]		= BCM_6345_DSL_IRQ,
 	[IRQ_ENET0]		= BCM_6345_ENET0_IRQ,
 	[IRQ_ENET_PHY]		= BCM_6345_ENET_PHY_IRQ,
+	[IRQ_ENET0_RXDMA]	= BCM_6345_ENET0_RXDMA_IRQ,
+	[IRQ_ENET0_TXDMA]	= BCM_6345_ENET0_TXDMA_IRQ,
 };
 
 /*
@@ -288,6 +306,9 @@ static unsigned int detect_memory_size(void)
 	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
 	u32 val;
 
+	if (BCMCPU_IS_6345())
+		return (8 * 1024 * 1024);
+
 	if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
 		val = bcm_sdram_readl(SDRAM_CFG_REG);
 		rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;