X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=target%2Flinux%2Far71xx%2Fpatches-3.6%2F609-MIPS-ath79-ap136-fixes.patch;h=6358e478074924dc86ab98b6b0c1fb04cd1c56ff;hb=e1965a1d1a8e98673c5851ea42e191f4ebd7bf4f;hp=33d807392107b321b370e8311269b343766bebdb;hpb=a0b31f97bb215b2de2c4addbc426121511f1d625;p=oweals%2Fopenwrt.git diff --git a/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch index 33d8073921..6358e47807 100644 --- a/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch +++ b/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch @@ -7,7 +7,7 @@ * * Copyright (c) 2012 Qualcomm Atheros * Copyright (c) 2012 Gabor Juhos -@@ -18,23 +18,27 @@ +@@ -18,23 +18,28 @@ * */ @@ -26,6 +26,7 @@ #include "dev-leds-gpio.h" -#include "dev-spi.h" +#include "dev-m25p80.h" ++#include "dev-nfc.h" #include "dev-usb.h" #include "dev-wmac.h" -#include "pci.h" @@ -43,7 +44,7 @@ #define AP136_GPIO_LED_WPS_GREEN 20 #define AP136_GPIO_BTN_WPS 16 -@@ -43,8 +47,10 @@ +@@ -43,8 +48,10 @@ #define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ #define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) @@ -56,94 +57,90 @@ static struct gpio_led ap136_leds_gpio[] __initdata = { { -@@ -98,63 +104,91 @@ static struct gpio_keys_button ap136_gpi +@@ -98,64 +105,158 @@ static struct gpio_keys_button ap136_gpi }, }; -static struct ath79_spi_controller_data ap136_spi0_data = { - .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, - .cs_line = 0, -+static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg = { -+ .mode = AR8327_PAD_MAC_RGMII, -+ .txclk_delay_en = true, -+ .rxclk_delay_en = true, -+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, -+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, ++static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg; ++static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg; ++ ++static struct ar8327_platform_data ap136_ar8327_data = { ++ .pad0_cfg = &ap136_ar8327_pad0_cfg, ++ .pad6_cfg = &ap136_ar8327_pad6_cfg, ++ .port0_cfg = { ++ .force_link = 1, ++ .speed = AR8327_PORT_SPEED_1000, ++ .duplex = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ }, ++ .port6_cfg = { ++ .force_link = 1, ++ .speed = AR8327_PORT_SPEED_1000, ++ .duplex = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ }, }; -static struct spi_board_info ap136_spi_info[] = { -- { ++static struct mdio_board_info ap136_mdio0_info[] = { + { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "mx25l6405d", - .controller_data = &ap136_spi0_data, - } -+static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg = { -+ .mode = AR8327_PAD_MAC_SGMII, -+ .txclk_delay_en = false, -+ .rxclk_delay_en = true, -+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL0, -+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, ++ .bus_id = "ag71xx-mdio.0", ++ .phy_addr = 0, ++ .platform_data = &ap136_ar8327_data, ++ }, }; -static struct ath79_spi_platform_data ap136_spi_data = { - .bus_num = 0, - .num_chipselect = 1, -+static struct ar8327_platform_data ap136_ar8327_data = { -+ .pad0_cfg = &ap136_ar8327_pad0_cfg, -+ .pad6_cfg = &ap136_ar8327_pad6_cfg, -+ .port0_cfg = { -+ .force_link = 1, -+ .speed = AR8327_PORT_SPEED_1000, -+ .duplex = 1, -+ .txpause = 1, -+ .rxpause = 1, -+ } - }; +-}; ++static void __init ap136_gmac_setup(void) ++{ ++ void __iomem *base; ++ u32 t; -#ifdef CONFIG_PCI -static struct ath9k_platform_data ap136_ath9k_data; -+static struct mdio_board_info ap136_mdio0_info[] = { -+ { -+ .bus_id = "ag71xx-mdio.0", -+ .phy_addr = 0, -+ .platform_data = &ap136_ar8327_data, -+ }, -+}; ++ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); -static int ap136_pci_plat_dev_init(struct pci_dev *dev) -+static void __init ap136_gmac_setup(void) - { +-{ - if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0) - dev->dev.platform_data = &ap136_ath9k_data; -+ void __iomem *base; -+ u32 t; ++ t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG); - return 0; -} -+ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); ++ t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII); ++ t |= QCA955X_ETH_CFG_RGMII_EN; -static void __init ap136_pci_init(u8 *eeprom) -{ - memcpy(ap136_ath9k_data.eeprom_data, eeprom, - sizeof(ap136_ath9k_data.eeprom_data)); -+ t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG); -+ -+ t &= ~(QCA955X_ETH_CFG_RGMII_GMAC0 | QCA955X_ETH_CFG_SGMII_GMAC0); -+ t |= QCA955X_ETH_CFG_RGMII_GMAC0; ++ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); - ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); - ath79_register_pci(); -+ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); -+ + iounmap(base); } -#else -static inline void ap136_pci_init(void) {} -#endif /* CONFIG_PCI */ - static void __init ap136_setup(void) +-static void __init ap136_setup(void) ++static void __init ap136_common_setup(void) { u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); @@ -160,6 +157,8 @@ ath79_register_usb(); - ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET); - ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET); ++ ath79_register_nfc(); ++ + ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL); + ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL); + @@ -172,13 +171,121 @@ + mdiobus_register_board_info(ap136_mdio0_info, + ARRAY_SIZE(ap136_mdio0_info)); + -+ /* GMAC0 is connected to an AR8327 switch */ ++ /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; -+ ath79_eth0_pll_data.pll_1000 = 0xa6000000; + + ath79_register_eth(0); ++ ++ /* GMAC1 is connected tot eh SGMII interface */ ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ++ ath79_eth1_data.speed = SPEED_1000; ++ ath79_eth1_data.duplex = DUPLEX_FULL; ++ ++ ath79_register_eth(1); ++} ++ ++static void __init ap136_010_setup(void) ++{ ++ /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */ ++ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII; ++ ap136_ar8327_pad0_cfg.txclk_delay_en = true; ++ ap136_ar8327_pad0_cfg.rxclk_delay_en = true; ++ ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; ++ ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; ++ ++ /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */ ++ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII; ++ ap136_ar8327_pad6_cfg.rxclk_delay_en = true; ++ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0; ++ ++ ath79_eth0_pll_data.pll_1000 = 0xa6000000; ++ ath79_eth1_pll_data.pll_1000 = 0x03000101; ++ ++ ap136_common_setup(); ++} ++ ++MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", ++ "Atheros AP136-010 reference board", ++ ap136_010_setup); ++ ++static void __init ap136_020_setup(void) ++{ ++ /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */ ++ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII; ++ ap136_ar8327_pad0_cfg.sgmii_delay_en = true; ++ ++ /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */ ++ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII; ++ ap136_ar8327_pad6_cfg.txclk_delay_en = true; ++ ap136_ar8327_pad6_cfg.rxclk_delay_en = true; ++ ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; ++ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; ++ ++ ath79_eth0_pll_data.pll_1000 = 0x56000000; ++ ath79_eth1_pll_data.pll_1000 = 0x03000101; ++ ++ ap136_common_setup(); ++} ++ ++MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020", ++ "Atheros AP136-020 reference board", ++ ap136_020_setup); ++ ++/* ++ * AP135-020 is similar to AP136-020, any future AP135 specific init ++ * code can be added here. ++ */ ++static void __init ap135_020_setup(void) ++{ ++ ap136_leds_gpio[0].name = "ap135:green:status"; ++ ap136_leds_gpio[1].name = "ap135:red:status"; ++ ap136_leds_gpio[2].name = "ap135:green:wps"; ++ ap136_leds_gpio[3].name = "ap135:red:wps"; ++ ap136_leds_gpio[4].name = "ap135:red:wlan-2g"; ++ ap136_leds_gpio[5].name = "ap135:red:usb"; ++ ++ ap136_020_setup(); } - MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board", +-MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board", +- ap136_setup); ++MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020", ++ "Atheros AP135-020 reference board", ++ ap135_020_setup); +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -18,7 +18,9 @@ enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP121, /* Atheros AP121 reference board */ + ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */ +- ATH79_MACH_AP136, /* Atheros AP136 reference board */ ++ ATH79_MACH_AP135_020, /* Atheros AP135-020 reference board */ ++ ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ ++ ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -16,16 +16,17 @@ config ATH79_MACH_AP121 + Atheros AP121 reference board. + + config ATH79_MACH_AP136 +- bool "Atheros AP136 reference board" ++ bool "Atheros AP136/AP135 reference board" + select SOC_QCA955X + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_NFC + select ATH79_DEV_SPI + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help + Say 'Y' here if you want your kernel to support the +- Atheros AP136 reference board. ++ Atheros AP136 or AP135 reference boards. + + config ATH79_MACH_AP81 + bool "Atheros AP81 reference board"