X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=nand_spl%2Fnand_boot.c;h=ccd0af25548e7520c594b698dfebdcf46b1474b2;hb=5e7efccdd38335a00616f62554e7958bc6668a41;hp=21abb09e39b52acf67eeea81fa3d6eb65382f7a3;hpb=64cd52efd1dc51a4a5a0cf10efe5362fab27de29;p=oweals%2Fu-boot.git diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index 21abb09e39..ccd0af2554 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -20,120 +20,199 @@ #include #include +#include -#define CFG_NAND_READ_DELAY \ +#define CONFIG_SYS_NAND_READ_DELAY \ { volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; } -extern void board_nand_init(struct nand_chip *nand); -extern void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd); -extern void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte); -extern u_char ndfc_read_byte(struct mtd_info *mtdinfo); -extern int ndfc_dev_ready(struct mtd_info *mtdinfo); -extern int jump_to_ram(ulong delta); -extern int jump_to_uboot(ulong addr); +static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; -static int nand_is_bad_block(struct mtd_info *mtd, int block) +#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512) +/* + * NAND command for small page NAND devices (512) + */ +static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd) { - struct nand_chip *this = mtd->priv; - int page_addr = block * CFG_NAND_PAGE_COUNT; + struct nand_chip *this = mtd->priv; + int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + + if (this->dev_ready) + while (!this->dev_ready(mtd)) + ; + else + CONFIG_SYS_NAND_READ_DELAY; /* Begin command latch cycle */ - this->hwcontrol(mtd, NAND_CTL_SETCLE); - this->write_byte(mtd, NAND_CMD_READOOB); + this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); /* Set ALE and clear CLE to start address cycle */ - this->hwcontrol(mtd, NAND_CTL_CLRCLE); - this->hwcontrol(mtd, NAND_CTL_SETALE); /* Column address */ - this->write_byte(mtd, CFG_NAND_BAD_BLOCK_POS); /* A[7:0] */ - this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */ - this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */ -#ifdef CFG_NAND_4_ADDR_CYCLE + this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE); + this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */ + this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff, + NAND_CTRL_ALE); /* A[24:17] */ +#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE /* One more address cycle for devices > 32MiB */ - this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */ + this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, + NAND_CTRL_ALE); /* A[28:25] */ #endif /* Latch in address */ - this->hwcontrol(mtd, NAND_CTL_CLRALE); + this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); /* * Wait a while for the data to be ready */ if (this->dev_ready) - this->dev_ready(mtd); + while (!this->dev_ready(mtd)) + ; else - CFG_NAND_READ_DELAY; - - /* - * Read on byte - */ - if (this->read_byte(mtd) != 0xff) - return 1; + CONFIG_SYS_NAND_READ_DELAY; return 0; } - -static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst) +#else +/* + * NAND command for large page NAND devices (2k) + */ +static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd) { - struct nand_chip *this = mtd->priv; - int page_addr = page + block * CFG_NAND_PAGE_COUNT; - int i; + struct nand_chip *this = mtd->priv; + int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + + if (this->dev_ready) + while (!this->dev_ready(mtd)) + ; + else + CONFIG_SYS_NAND_READ_DELAY; + + /* Emulate NAND_CMD_READOOB */ + if (cmd == NAND_CMD_READOOB) { + offs += CONFIG_SYS_NAND_PAGE_SIZE; + cmd = NAND_CMD_READ0; + } /* Begin command latch cycle */ - this->hwcontrol(mtd, NAND_CTL_SETCLE); - this->write_byte(mtd, NAND_CMD_READ0); + this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); /* Set ALE and clear CLE to start address cycle */ - this->hwcontrol(mtd, NAND_CTL_CLRCLE); - this->hwcontrol(mtd, NAND_CTL_SETALE); /* Column address */ - this->write_byte(mtd, 0); /* A[7:0] */ - this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */ - this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */ -#ifdef CFG_NAND_4_ADDR_CYCLE - /* One more address cycle for devices > 32MiB */ - this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */ + this->cmd_ctrl(mtd, offs & 0xff, + NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ + this->cmd_ctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ + /* Row address */ + this->cmd_ctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ + this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff), + NAND_CTRL_ALE); /* A[27:20] */ +#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE + /* One more address cycle for devices > 128MiB */ + this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, + NAND_CTRL_ALE); /* A[31:28] */ #endif /* Latch in address */ - this->hwcontrol(mtd, NAND_CTL_CLRALE); + this->cmd_ctrl(mtd, NAND_CMD_READSTART, + NAND_CTRL_CLE | NAND_CTRL_CHANGE); + this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); /* * Wait a while for the data to be ready */ if (this->dev_ready) - this->dev_ready(mtd); + while (!this->dev_ready(mtd)) + ; else - CFG_NAND_READ_DELAY; + CONFIG_SYS_NAND_READ_DELAY; + + return 0; +} +#endif + +static int nand_is_bad_block(struct mtd_info *mtd, int block) +{ + struct nand_chip *this = mtd->priv; + + nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); /* - * Read page into buffer + * Read one byte */ - for (i=0; iread_byte(mtd); + if (readb(this->IO_ADDR_R) != 0xff) + return 1; return 0; } -static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst) +static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst) { - int block; - int blockcopy_count; - int page; + struct nand_chip *this = mtd->priv; + u_char *ecc_calc; + u_char *ecc_code; + u_char *oob_data; + int i; + int eccsize = CONFIG_SYS_NAND_ECCSIZE; + int eccbytes = CONFIG_SYS_NAND_ECCBYTES; + int eccsteps = CONFIG_SYS_NAND_ECCSTEPS; + uint8_t *p = dst; + int stat; + + nand_command(mtd, block, page, 0, NAND_CMD_READ0); + + /* No malloc available for now, just use some temporary locations + * in SDRAM + */ + ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000); + ecc_code = ecc_calc + 0x100; + oob_data = ecc_calc + 0x200; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + this->ecc.hwctl(mtd, NAND_ECC_READ); + this->read_buf(mtd, p, eccsize); + this->ecc.calculate(mtd, p, &ecc_calc[i]); + } + this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); + + /* Pick the ECC bytes out of the oob data */ + for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++) + ecc_code[i] = oob_data[nand_ecc_pos[i]]; + + eccsteps = CONFIG_SYS_NAND_ECCSTEPS; + p = dst; + + for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + /* No chance to do something with the possible error message + * from correct_data(). We just hope that all possible errors + * are corrected by this routine. + */ + stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); + } + + return 0; +} + +static int nand_load(struct mtd_info *mtd, unsigned int offs, + unsigned int uboot_size, uchar *dst) +{ + unsigned int block, lastblock; + unsigned int page; /* - * offs has to be aligned to a block address! + * offs has to be aligned to a page address! */ - block = offs / CFG_NAND_BLOCK_SIZE; - blockcopy_count = 0; + block = offs / CONFIG_SYS_NAND_BLOCK_SIZE; + lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE; + page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE; - while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) { + while (block <= lastblock) { if (!nand_is_bad_block(mtd, block)) { /* * Skip bad blocks */ - for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) { + while (page < CONFIG_SYS_NAND_PAGE_COUNT) { nand_read_page(mtd, block, page, dst); - dst += CFG_NAND_PAGE_SIZE; + dst += CONFIG_SYS_NAND_PAGE_SIZE; + page++; } - blockcopy_count++; + page = 0; + } else { + lastblock++; } block++; @@ -142,36 +221,59 @@ static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst) return 0; } +#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +void board_init_f (ulong bootflag) +{ + relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, + CONFIG_SYS_TEXT_BASE); +} +#endif + +/* + * The main entry for NAND booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from NAND into SDRAM and starts it from there. + */ void nand_boot(void) { - ulong mem_size; struct nand_chip nand_chip; nand_info_t nand_info; int ret; - void (*uboot)(void); - - /* - * Init sdram, so we have access to memory - */ - mem_size = initdram(0); + __attribute__((noreturn)) void (*uboot)(void); /* * Init board specific nand support */ nand_info.priv = &nand_chip; - nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CFG_NAND_BASE; + nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; nand_chip.dev_ready = NULL; /* preset to NULL */ board_nand_init(&nand_chip); + if (nand_chip.select_chip) + nand_chip.select_chip(&nand_info, 0); + /* * Load U-Boot image from NAND into RAM */ - ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE, - (uchar *)CFG_NAND_U_BOOT_DST); + ret = nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); + +#ifdef CONFIG_NAND_ENV_DST + nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_NAND_ENV_DST); + +#ifdef CONFIG_ENV_OFFSET_REDUND + nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, + (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); +#endif +#endif + + if (nand_chip.select_chip) + nand_chip.select_chip(&nand_info, -1); /* * Jump to U-Boot image */ - uboot = (void (*)(void))CFG_NAND_U_BOOT_START; + uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; (*uboot)(); }