X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fusb%2Fehci-fsl.h;h=e9349b5c1666db1838ef8da34d194ee5c83bbb16;hb=b2016133edec9ece02dca7881e2e0c059d2b421c;hp=734305b9dba25fd1e1809e96db81781da0ea1659;hpb=509dca7a11aad394d781a9d31a7bfa6692562741;p=oweals%2Fu-boot.git

diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 734305b9db..e9349b5c16 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -11,6 +11,8 @@
 
 #include <asm/processor.h>
 
+#define CONTROL_REGISTER_W1C_MASK       0x00020000  /* W1C: PHY_CLK_VALID */
+
 /* Global offsets */
 #define FSL_SKIP_PCI		0x100
 
@@ -161,8 +163,18 @@
 #elif defined(CONFIG_MPC512X)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR	0
+#elif defined(CONFIG_LS102XA)
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR        0
 #endif
 
+/*
+ * Increasing TX FIFO threshold value from 2 to 4 decreases
+ * data burst rate with which data packets are posted from the TX
+ * latency FIFO to compensate for latencies in DDR pipeline during DMA
+ */
+#define TXFIFOTHRESH		4
+
 /*
  * USB Registers
  */
@@ -268,7 +280,9 @@ struct usb_ehci {
 #define MXC_EHCI_IPPUE_DOWN		(1 << 10)
 #define MXC_EHCI_IPPUE_UP		(1 << 11)
 
+int usb_phy_mode(int port);
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);
+int board_usb_phy_mode(int port);
 
 #endif /* _EHCI_FSL_H */