X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Ftsec.h;h=0ac303406060565543825748f9edb6177dd8d683;hb=73db0c71da365a2d101878ae3aeb8ff3545a1828;hp=83863aef16299d534820eaefb11f76403e229a44;hpb=dd3d1f56a01f460d560766126ee7dfed2ea9bc10;p=oweals%2Fu-boot.git

diff --git a/include/tsec.h b/include/tsec.h
index 83863aef16..0ac3034060 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -20,19 +20,35 @@
 #include <net.h>
 #include <config.h>
 
-#ifndef CFG_TSEC1_OFFSET
-    #define CFG_TSEC1_OFFSET	(0x24000)
+#ifndef CONFIG_SYS_TSEC1_OFFSET
+    #define CONFIG_SYS_TSEC1_OFFSET	(0x24000)
 #endif
 
 #define TSEC_SIZE	0x01000
 
 /* FIXME:  Should these be pushed back to 83xx and 85xx config files? */
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
-    #define TSEC_BASE_ADDR	(CFG_IMMR + CFG_TSEC1_OFFSET)
-#elif defined(CONFIG_MPC83XX)
-    #define TSEC_BASE_ADDR	(CFG_IMMR + CFG_TSEC1_OFFSET)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \
+	|| defined(CONFIG_MPC83xx)
+    #define TSEC_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #endif
 
+#define STD_TSEC_INFO(num) \
+{			\
+	.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
+	.miiregs = (tsec_t *)TSEC_BASE_ADDR, \
+	.devname = CONFIG_TSEC##num##_NAME, \
+	.phyaddr = TSEC##num##_PHY_ADDR, \
+	.flags = TSEC##num##_FLAGS \
+}
+
+#define SET_STD_TSEC_INFO(x, num) \
+{			\
+	x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
+	x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \
+	x.devname = CONFIG_TSEC##num##_NAME; \
+	x.phyaddr = TSEC##num##_PHY_ADDR; \
+	x.flags = TSEC##num##_FLAGS;\
+}
 
 #define MAC_ADDR_LEN 6
 
@@ -42,6 +58,27 @@
 
 #define PHY_AUTONEGOTIATE_TIMEOUT	5000 /* in ms */
 
+/* TBI register addresses */
+#define TBI_CR			0x00
+#define TBI_SR			0x01
+#define TBI_ANA			0x04
+#define TBI_ANLPBPA		0x05
+#define TBI_ANEX		0x06
+#define TBI_TBICON		0x11
+
+/* TBI MDIO register bit fields*/
+#define TBICON_CLK_SELECT	0x0020
+#define TBIANA_ASYMMETRIC_PAUSE 0x0100
+#define TBIANA_SYMMETRIC_PAUSE  0x0080
+#define TBIANA_HALF_DUPLEX	0x0040
+#define TBIANA_FULL_DUPLEX	0x0020
+#define TBICR_PHY_RESET		0x8000
+#define TBICR_ANEG_ENABLE	0x1000
+#define TBICR_RESTART_ANEG	0x0200
+#define TBICR_FULL_DUPLEX	0x0100
+#define TBICR_SPEED1_SET	0x0040
+
+
 /* MAC register bits */
 #define MACCFG1_SOFT_RESET	0x80000000
 #define MACCFG1_RESET_RX_MC	0x00080000
@@ -70,8 +107,8 @@
 #define miim_end -2
 #define miim_read -1
 
-#ifndef CFG_TBIPA_VALUE
-    #define CFG_TBIPA_VALUE	0x1f
+#ifndef CONFIG_SYS_TBIPA_VALUE
+    #define CONFIG_SYS_TBIPA_VALUE	0x1f
 #endif
 #define MIIMCFG_INIT_VALUE	0x00000003
 #define MIIMCFG_RESET		0x80000000
@@ -115,6 +152,8 @@
 #define MIIM_EXT_PAGE_ACCESS	0x1f
 
 /* Broadcom BCM54xx -- taken from linux sungem_phy */
+#define MIIM_BCM54xx_AUXCNTL			0x18
+#define MIIM_BCM54xx_AUXCNTL_ENCODE(val)	((val & 0x7) << 12)|(val & 0x7)
 #define MIIM_BCM54xx_AUXSTATUS			0x19
 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK	0x0700
 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT	8
@@ -189,6 +228,10 @@
 #define MIIM_88E1121_PHY_LED_PAGE	3
 #define MIIM_88E1121_PHY_LED_DEF	0x0030
 
+/* 88E1121 PHY IRQ Enable/Status Register */
+#define MIIM_88E1121_PHY_IRQ_EN		18
+#define MIIM_88E1121_PHY_IRQ_STATUS	19
+
 #define MIIM_88E1121_PHY_PAGE		22
 
 /* 88E1145 Extended PHY Specific Control Register */
@@ -522,7 +565,9 @@ typedef struct tsec
 
 /* This flag currently only has
  * meaning if we're using the eTSEC */
-#define TSEC_REDUCED (1 << 1)
+#define TSEC_REDUCED	(1 << 1)
+
+#define TSEC_SGMII	(1 << 2)
 
 struct tsec_private {
 	volatile tsec_t *regs;
@@ -584,9 +629,15 @@ struct phy_info {
 };
 
 struct tsec_info_struct {
+	tsec_t *regs;
+	tsec_t *miiregs;
+	char *devname;
 	unsigned int phyaddr;
 	u32 flags;
-	unsigned int phyregidx;
 };
 
+int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
+int tsec_standard_init(bd_t *bis);
+int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
+
 #endif /* __TSEC_H */