X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Ftsec.h;h=0ac303406060565543825748f9edb6177dd8d683;hb=73db0c71da365a2d101878ae3aeb8ff3545a1828;hp=2db4debfbb4a536cab79e0e21e7e832b04ab1fe8;hpb=16116ddd0d0158f4e91c91dc979b845b6e98a99d;p=oweals%2Fu-boot.git

diff --git a/include/tsec.h b/include/tsec.h
index 2db4debfbb..0ac3034060 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -20,16 +20,16 @@
 #include <net.h>
 #include <config.h>
 
-#ifndef CFG_TSEC1_OFFSET
-    #define CFG_TSEC1_OFFSET	(0x24000)
+#ifndef CONFIG_SYS_TSEC1_OFFSET
+    #define CONFIG_SYS_TSEC1_OFFSET	(0x24000)
 #endif
 
 #define TSEC_SIZE	0x01000
 
 /* FIXME:  Should these be pushed back to 83xx and 85xx config files? */
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \
-	|| defined(CONFIG_MPC83XX)
-    #define TSEC_BASE_ADDR	(CFG_IMMR + CFG_TSEC1_OFFSET)
+	|| defined(CONFIG_MPC83xx)
+    #define TSEC_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #endif
 
 #define STD_TSEC_INFO(num) \
@@ -50,8 +50,6 @@
 	x.flags = TSEC##num##_FLAGS;\
 }
 
-
-
 #define MAC_ADDR_LEN 6
 
 /* #define TSEC_TIMEOUT	1000000 */
@@ -109,8 +107,8 @@
 #define miim_end -2
 #define miim_read -1
 
-#ifndef CFG_TBIPA_VALUE
-    #define CFG_TBIPA_VALUE	0x1f
+#ifndef CONFIG_SYS_TBIPA_VALUE
+    #define CONFIG_SYS_TBIPA_VALUE	0x1f
 #endif
 #define MIIMCFG_INIT_VALUE	0x00000003
 #define MIIMCFG_RESET		0x80000000
@@ -154,6 +152,8 @@
 #define MIIM_EXT_PAGE_ACCESS	0x1f
 
 /* Broadcom BCM54xx -- taken from linux sungem_phy */
+#define MIIM_BCM54xx_AUXCNTL			0x18
+#define MIIM_BCM54xx_AUXCNTL_ENCODE(val)	((val & 0x7) << 12)|(val & 0x7)
 #define MIIM_BCM54xx_AUXSTATUS			0x19
 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK	0x0700
 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT	8
@@ -228,6 +228,10 @@
 #define MIIM_88E1121_PHY_LED_PAGE	3
 #define MIIM_88E1121_PHY_LED_DEF	0x0030
 
+/* 88E1121 PHY IRQ Enable/Status Register */
+#define MIIM_88E1121_PHY_IRQ_EN		18
+#define MIIM_88E1121_PHY_IRQ_STATUS	19
+
 #define MIIM_88E1121_PHY_PAGE		22
 
 /* 88E1145 Extended PHY Specific Control Register */