X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fppc440.h;h=54b455313957d86eda48c4d75dea82dadf9d574e;hb=53677ef18e25c97ac613349087c5cb33ae5a2741;hp=10517cbb6509e3fd9dd6e3500e79566ea5dde4ba;hpb=3d61018643a2cd38c145aa6dde53f3f5f1a0e9cf;p=oweals%2Fu-boot.git

diff --git a/include/ppc440.h b/include/ppc440.h
index 10517cbb65..54b4553139 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1437,6 +1437,13 @@
 #define GPT0_COMP2			0x00000088
 #define GPT0_COMP1			0x00000084
 
+#define GPT0_MASK6			0x000000D8
+#define GPT0_MASK5			0x000000D4
+#define GPT0_MASK4			0x000000D0
+#define GPT0_MASK3			0x000000CC
+#define GPT0_MASK2			0x000000C8
+#define GPT0_MASK1			0x000000C4
+
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define SDR0_USB2D0CR                 0x0320
 #define   SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK   0x00000004    /* USB 2.0 Device/EBC Master Selection */
@@ -1731,17 +1738,10 @@
 #else
 #define CNTRL_DCR_BASE 0x0b0
 #endif
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
 #define cpc0_er		(CNTRL_DCR_BASE+0x00)	/* CPM enable register		*/
 #define cpc0_fr		(CNTRL_DCR_BASE+0x01)	/* CPM force register		*/
 #define cpc0_sr		(CNTRL_DCR_BASE+0x02)	/* CPM status register		*/
-#else
-#define cpc0_sr		(CNTRL_DCR_BASE+0x00)	/* CPM status register		*/
-#define cpc0_er		(CNTRL_DCR_BASE+0x01)	/* CPM enable register		*/
-#define cpc0_fr		(CNTRL_DCR_BASE+0x02)	/* CPM force register		*/
-#endif
 
 #define cpc0_sys0	(CNTRL_DCR_BASE+0x30)	/* System configuration reg 0	*/
 #define cpc0_sys1	(CNTRL_DCR_BASE+0x31)	/* System configuration reg 1	*/
@@ -2023,9 +2023,13 @@
 #define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg   */
 #define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg   */
 #define malrxctp8r  (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg   */
+#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg  */
+#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg  */
 #define malrcbs2    (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg	    */
 #define malrcbs3    (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg	    */
 #define malrcbs8    (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg	    */
+#define malrcbs16   (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg    */
+#define malrcbs24   (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg    */
 #endif /* CONFIG_440GX */
 
 
@@ -2159,7 +2163,7 @@
 #define UIC_UIC3NC	0x00008000	/* UIC3 non-critical interrupt	    */
 #define UIC_UIC3C	0x00004000	/* UIC3 critical interrupt	    */
 #define UIC_EIR1	0x00002000	/* External interrupt 1		    */
-#define UIC_TRNGDA	0x00001000	/* TRNG data available 		    */
+#define UIC_TRNGDA	0x00001000	/* TRNG data available		    */
 #define UIC_PKAR1	0x00000800	/* PKA ready (PKA[1])		    */
 #define UIC_D1CPFF	0x00000400	/* DMA1 cp fifo full		    */
 #define UIC_D1CSNS	0x00000200	/* DMA1 cs fifo needs service	    */