X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fphy.h;h=d01435d1aa1a2a720de3cd7d930ba88e7eef46e0;hb=1f1075c6e385a746d58d2ca0cd2f2f9dde1c2f5d;hp=8e507cd7a68584098ed45e937dab075e6e80062f;hpb=d11e9347461cff9ce89e6e65764f73fad0f19c6f;p=oweals%2Fu-boot.git diff --git a/include/phy.h b/include/phy.h index 8e507cd7a6..d01435d1aa 100644 --- a/include/phy.h +++ b/include/phy.h @@ -1,19 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011 Freescale Semiconductor, Inc. * Andy Fleming * - * SPDX-License-Identifier: GPL-2.0+ - * * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h */ #ifndef _PHY_H #define _PHY_H +#include #include #include #include #include +#include + +#define PHY_FIXED_ID 0xa5a55a5a #define PHY_MAX_ADDR 32 @@ -47,58 +50,6 @@ #endif -typedef enum { - PHY_INTERFACE_MODE_MII, - PHY_INTERFACE_MODE_GMII, - PHY_INTERFACE_MODE_SGMII, - PHY_INTERFACE_MODE_SGMII_2500, - PHY_INTERFACE_MODE_QSGMII, - PHY_INTERFACE_MODE_TBI, - PHY_INTERFACE_MODE_RMII, - PHY_INTERFACE_MODE_RGMII, - PHY_INTERFACE_MODE_RGMII_ID, - PHY_INTERFACE_MODE_RGMII_RXID, - PHY_INTERFACE_MODE_RGMII_TXID, - PHY_INTERFACE_MODE_RTBI, - PHY_INTERFACE_MODE_XGMII, - PHY_INTERFACE_MODE_XAUI, - PHY_INTERFACE_MODE_RXAUI, - PHY_INTERFACE_MODE_SFI, - PHY_INTERFACE_MODE_NONE, /* Must be last */ - - PHY_INTERFACE_MODE_COUNT, -} phy_interface_t; - -static const char *phy_interface_strings[] = { - [PHY_INTERFACE_MODE_MII] = "mii", - [PHY_INTERFACE_MODE_GMII] = "gmii", - [PHY_INTERFACE_MODE_SGMII] = "sgmii", - [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", - [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", - [PHY_INTERFACE_MODE_TBI] = "tbi", - [PHY_INTERFACE_MODE_RMII] = "rmii", - [PHY_INTERFACE_MODE_RGMII] = "rgmii", - [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", - [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", - [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", - [PHY_INTERFACE_MODE_RTBI] = "rtbi", - [PHY_INTERFACE_MODE_XGMII] = "xgmii", - [PHY_INTERFACE_MODE_XAUI] = "xaui", - [PHY_INTERFACE_MODE_RXAUI] = "rxaui", - [PHY_INTERFACE_MODE_SFI] = "sfi", - [PHY_INTERFACE_MODE_NONE] = "", -}; - -static inline const char *phy_string_for_interface(phy_interface_t i) -{ - /* Default to unknown */ - if (i > PHY_INTERFACE_MODE_NONE) - i = PHY_INTERFACE_MODE_NONE; - - return phy_interface_strings[i]; -} - - struct phy_device; #define MDIO_NAME_LEN 32 @@ -150,6 +101,14 @@ struct phy_driver { int (*readext)(struct phy_device *phydev, int addr, int devad, int reg); int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg, u16 val); + + /* Phy specific driver override for reading a MMD register */ + int (*read_mmd)(struct phy_device *phydev, int devad, int reg); + + /* Phy specific driver override for writing a MMD register */ + int (*write_mmd)(struct phy_device *phydev, int devad, int reg, + u16 val); + struct list_head list; }; @@ -162,6 +121,7 @@ struct phy_device { #ifdef CONFIG_DM_ETH struct udevice *dev; + ofnode node; #else struct eth_device *dev; #endif @@ -186,6 +146,7 @@ struct phy_device { int pause; int asym_pause; u32 phy_id; + bool is_c45; u32 flags; }; @@ -212,6 +173,68 @@ static inline int phy_write(struct phy_device *phydev, int devad, int regnum, return bus->write(bus, phydev->addr, devad, regnum, val); } +static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad, + int regnum) +{ + /* Write the desired MMD Devad */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum); + + /* Select the Function : DATA with no post increment */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, + (devad | MII_MMD_CTRL_NOINCR)); +} + +static inline int phy_read_mmd(struct phy_device *phydev, int devad, + int regnum) +{ + struct phy_driver *drv = phydev->drv; + + if (regnum > (u16)~0 || devad > 32) + return -EINVAL; + + /* driver-specific access */ + if (drv->read_mmd) + return drv->read_mmd(phydev, devad, regnum); + + /* direct C45 / C22 access */ + if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES || + devad == MDIO_DEVAD_NONE || !devad) + return phy_read(phydev, devad, regnum); + + /* indirect C22 access */ + phy_mmd_start_indirect(phydev, devad, regnum); + + /* Read the content of the MMD's selected register */ + return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA); +} + +static inline int phy_write_mmd(struct phy_device *phydev, int devad, + int regnum, u16 val) +{ + struct phy_driver *drv = phydev->drv; + + if (regnum > (u16)~0 || devad > 32) + return -EINVAL; + + /* driver-specific access */ + if (drv->write_mmd) + return drv->write_mmd(phydev, devad, regnum, val); + + /* direct C45 / C22 access */ + if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES || + devad == MDIO_DEVAD_NONE || !devad) + return phy_write(phydev, devad, regnum, val); + + /* indirect C22 access */ + phy_mmd_start_indirect(phydev, devad, regnum); + + /* Write the data into MMD's selected register */ + return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val); +} + #ifdef CONFIG_PHYLIB_10G extern struct phy_driver gen10g_driver; @@ -232,11 +255,22 @@ void phy_connect_dev(struct phy_device *phydev, struct udevice *dev); struct phy_device *phy_connect(struct mii_dev *bus, int addr, struct udevice *dev, phy_interface_t interface); +static inline ofnode phy_get_ofnode(struct phy_device *phydev) +{ + if (ofnode_valid(phydev->node)) + return phydev->node; + else + return dev_ofnode(phydev->dev); +} #else void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); struct phy_device *phy_connect(struct mii_dev *bus, int addr, struct eth_device *dev, phy_interface_t interface); +static inline ofnode phy_get_ofnode(struct phy_device *phydev) +{ + return ofnode_null(); +} #endif int phy_startup(struct phy_device *phydev); int phy_config(struct phy_device *phydev); @@ -255,6 +289,7 @@ int gen10g_startup(struct phy_device *phydev); int gen10g_shutdown(struct phy_device *phydev); int gen10g_discover_mmds(struct phy_device *phydev); +int phy_b53_init(void); int phy_mv88e61xx_init(void); int phy_aquantia_init(void); int phy_atheros_init(void); @@ -264,7 +299,9 @@ int phy_davicom_init(void); int phy_et1011c_init(void); int phy_lxt_init(void); int phy_marvell_init(void); -int phy_micrel_init(void); +int phy_micrel_ksz8xxx_init(void); +int phy_micrel_ksz90x1_init(void); +int phy_meson_gxl_init(void); int phy_natsemi_init(void); int phy_realtek_init(void); int phy_smsc_init(void); @@ -273,6 +310,7 @@ int phy_ti_init(void); int phy_vitesse_init(void); int phy_xilinx_init(void); int phy_mscc_init(void); +int phy_fixed_init(void); int board_phy_config(struct phy_device *phydev); int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); @@ -308,7 +346,9 @@ static inline bool phy_interface_is_sgmii(struct phy_device *phydev) } /* PHY UIDs for various PHYs that are referenced in external code */ -#define PHY_UID_CS4340 0x13e51002 -#define PHY_UID_TN2020 0x00a19410 +#define PHY_UID_CS4340 0x13e51002 +#define PHY_UID_CS4223 0x03e57003 +#define PHY_UID_TN2020 0x00a19410 +#define PHY_UID_IN112525_S03 0x02107440 #endif