X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fmpc8xx.h;h=fc081ab7568e76ae0c09508b11d0434eb9c704d8;hb=57da060755ac757237bd8781f7b2aef80167301e;hp=3650643704c7bc2f4f9154b90e7ddb810ee89477;hpb=1f4bb37d6bcae59b18a2438f3cdca6545a831ab5;p=oweals%2Fu-boot.git diff --git a/include/mpc8xx.h b/include/mpc8xx.h index 3650643704..fc081ab756 100644 --- a/include/mpc8xx.h +++ b/include/mpc8xx.h @@ -1,24 +1,8 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -35,7 +19,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ - +#define _START_OFFSET EXC_OFF_SYS_RESET /*----------------------------------------------------------------------- * SYPCR - System Protection Control Register 11-9 @@ -131,45 +115,43 @@ #define RSR_ALLBITS (RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS) +/*----------------------------------------------------------------------- + * Newer chips (MPC866 family and MPC87x/88x family) have different + * clock distribution system. Their IMMR lower half is >= 0x0800 + */ +#define MPC8xx_NEW_CLK 0x0800 + /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 */ -#ifdef CONFIG_MPC866_et_al -#define PLPRCR_MF_MSK 0xffff001e /* Multiplication factor + PDF bits */ -#define PLPRCR_MFN_MSK 0xf8000000 /* Multiplication factor numerator bits */ -#define PLPRCR_MFN_SHIFT 0x0000001b /* Multiplication factor numerator shift*/ -#define PLPRCR_MFD_MSK 0x03c00000 /* Multiplication factor denominator bits */ -#define PLPRCR_MFD_SHIFT 0x00000017 /* Multiplication factor denominator shift*/ +/* Newer chips (MPC866/87x/88x et al) defines */ +#define PLPRCR_MFN_MSK 0xF8000000 /* Multiplication factor numerator bits */ +#define PLPRCR_MFN_SHIFT 27 /* Multiplication factor numerator shift*/ +#define PLPRCR_MFD_MSK 0x07C00000 /* Multiplication factor denominator bits */ +#define PLPRCR_MFD_SHIFT 22 /* Multiplication factor denominator shift*/ #define PLPRCR_S_MSK 0x00300000 /* Multiplication factor integer bits */ -#define PLPRCR_S_SHIFT 0x00000014 /* Multiplication factor integer shift */ -#define PLPRCR_MFI_MSK 0x000f0000 /* Multiplication factor integer bits */ -#define PLPRCR_MFI_SHIFT 0x00000010 /* Multiplication factor integer shift */ -#else -#define PLPRCR_MF_MSK 0xfff00000 /* Multiplication factor bits */ -#define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */ -#endif -#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */ +#define PLPRCR_S_SHIFT 20 /* Multiplication factor integer shift */ +#define PLPRCR_MFI_MSK 0x000F0000 /* Multiplication factor integer bits */ +#define PLPRCR_MFI_SHIFT 16 /* Multiplication factor integer shift */ + +#define PLPRCR_PDF_MSK 0x0000001E /* Predivision Factor bits */ +#define PLPRCR_PDF_SHIFT 1 /* Predivision Factor shift value */ +#define PLPRCR_DBRMO 0x00000001 /* DPLL BRM Order bit */ + +/* Multiplication factor + PDF bits */ +#define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \ + PLPRCR_MFD_MSK | \ + PLPRCR_S_MSK | \ + PLPRCR_MFI_MSK | \ + PLPRCR_PDF_MSK) + +/* Common defines */ #define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ -#ifndef CONFIG_MPC866_et_al -#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */ -#endif #define PLPRCR_CSRC 0x00000400 /* Clock Source */ -#ifndef CONFIG_MPC866_et_al -#define PLPRCR_LPM_MSK 0x00000300 /* Low Power Mode mask */ -#define PLPRCR_LPM_NORMAL 0x00000000 /* normal power management mode */ -#define PLPRCR_LPM_DOZE 0x00000100 /* doze power management mode */ -#define PLPRCR_LPM_SLEEP 0x00000200 /* sleep power management mode */ -#define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode */ -#define PLPRCR_LPM_DOWN 0x00000300 /* down power management mode */ -#endif + #define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ #define PLPRCR_LOLRE 0x00000040 /* Loss Of Lock Reset Enable */ #define PLPRCR_FIOPD 0x00000020 /* Force I/O Pull Down */ -#ifdef CONFIG_MPC866_et_al -#define PLPRCR_PDF_MSK 0x0000001e /* Predivision Factor bits */ -#define PLPRCR_PDF_SHIFT 0x00000001 /* Predivision Factor shift value */ -#define PLPRCR_DBRMO 0x00000001 /* DPLL BRM Order bit */ -#endif /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -196,6 +178,12 @@ #define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */ #define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */ #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ +#define SCCR_DFNL001 0x00000100 /* Division by 4 */ +#define SCCR_DFNL010 0x00000200 /* Division by 8 */ +#define SCCR_DFNL011 0x00000300 /* Division by 16 */ +#define SCCR_DFNL100 0x00000400 /* Division by 32 */ +#define SCCR_DFNL101 0x00000500 /* Division by 64 */ +#define SCCR_DFNL110 0x00000600 /* Division by 128 */ #define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */ #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ #define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */