X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fmpc5xx.h;h=de6d215d35c7d58a82187357b2f0cc5955fd7d69;hb=52a8b82074d1c3a3dcde8e3d90e6a04f7eb3a1f8;hp=345fca8de31cf693359408f00ec50f10aaca89ad;hpb=8bde7f776c77b343aca29b8c7b58464d915ac245;p=oweals%2Fu-boot.git diff --git a/include/mpc5xx.h b/include/mpc5xx.h index 345fca8de3..de6d215d35 100644 --- a/include/mpc5xx.h +++ b/include/mpc5xx.h @@ -36,12 +36,13 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET EXC_OFF_SYS_RESET /*----------------------------------------------------------------------- * ISB bit in IMMR to set internal memory map */ -#define CFG_ISB ((CFG_IMMR / 0x00400000) << 1) +#define CONFIG_SYS_ISB ((CONFIG_SYS_IMMR / 0x00400000) << 1) /*----------------------------------------------------------------------- * SYPCR - System Protection Control Register @@ -75,6 +76,10 @@ #define SIUMCR_DBPC01 0x00080000 /* - " - */ #define SIUMCR_DBPC10 0x00100000 /* - " - */ #define SIUMCR_DBPC11 0x00180000 /* - " - */ +#define SIUMCR_GPC00 0x00000000 /* General Pins Config */ +#define SIUMCR_GPC01 0x00020000 /* General Pins Config */ +#define SIUMCR_GPC10 0x00040000 /* General Pins Config */ +#define SIUMCR_GPC11 0x00060000 /* General Pins Config */ #define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ #define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */ #define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */ @@ -85,7 +90,7 @@ #define SIUMCR_MLRC01 0x00000400 /* - " - */ #define SIUMCR_MLRC10 0x00000800 /* - " - */ #define SIUMCR_MLRC11 0x00000c00 /* - " - */ -#define SIUMCR_MTSC 0x00000100 /* Memory transfer */ +#define SIUMCR_MTSC 0x00000100 /* Memory transfer */ /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control Register @@ -98,6 +103,7 @@ * PISCR - Periodic Interrupt Status and Control Register */ #define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */ +#define PISCR_PS 0x0080 /* Periodic Interrupt Status */ /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register @@ -106,36 +112,39 @@ #define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */ #define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */ #define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */ -#define PLPRCR_DIVF_0 0x00900000 /* Division factor 0 */ -#define PLPRCR_MF_9 0x00000000 /* Mulitipliaction factor 9 */ +#define PLPRCR_DIVF_0 0x00000000 /* Division factor 0 */ +#define PLPRCR_MF_9 0x00900000 /* Mulitipliaction factor 9 */ #define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ #define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */ #define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ +#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register */ #define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */ -#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ +#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ #define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */ #define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */ #define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */ #define SCCR_EBDF11 0x00060000 /* reserved */ #define SCCR_TBS 0x02000000 /* Time Base Source */ -#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ +#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ #define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ +#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ /*----------------------------------------------------------------------- * MC - Memory Controller */ -#define BR_V 0x00000001 /* Bank valid */ -#define BR_BI 0x00000002 /* Burst inhibit */ -#define BR_PS_8 0x00000400 /* 8 bit port size */ -#define BR_PS_16 0x00000800 /* 16 bit port size */ -#define BR_PS_32 0x00000000 /* 32 bit port size */ +#define BR_V 0x00000001 /* Bank valid */ +#define BR_BI 0x00000002 /* Burst inhibit */ +#define BR_PS_8 0x00000400 /* 8 bit port size */ +#define BR_PS_16 0x00000800 /* 16 bit port size */ +#define BR_PS_32 0x00000000 /* 32 bit port size */ #define BR_LBDIR 0x00000008 /* Late burst data in progess */ +#define BR_SETA 0x00000004 /* External Data Acknowledge */ #define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */ #define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */ #define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */ @@ -143,15 +152,15 @@ #define OR_BSCY 0x00000060 /* Burst beats length in clocks */ #define OR_ACS_10 0x00000600 /* Adress to chip-select setup */ #define OR_CSNT 0x00000800 /* Chip-select negotation time */ -#define OR_ETHR 0x00000000 /* Extended hold time on read */ +#define OR_ETHR 0x00000100 /* Extended hold time on read */ #define OR_ADDR_MK_FF 0xFF000000 #define OR_ADDR_MK_FFFF 0xFFFF0000 /*----------------------------------------------------------------------- * UMCR - UIMB Module Configuration Register */ -#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */ -#define UMCR_HSPEED 0x10000000 /* Half speed */ +#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */ +#define UMCR_HSPEED 0x10000000 /* Half speed */ /*----------------------------------------------------------------------- * ICTRL - I-Bus Support Control Register @@ -165,16 +174,16 @@ * SCI - Serial communication interface */ -#define SCI_TDRE 0x0100 /* Transmit data register empty */ -#define SCI_TE 0x0008 /* Transmitter enabled */ +#define SCI_TDRE 0x0100 /* Transmit data register empty */ +#define SCI_TE 0x0008 /* Transmitter enabled */ #define SCI_RE 0x0004 /* Receiver enabled */ -#define SCI_RDRF 0x0040 /* Receive data register full */ -#define SCI_PE 0x0400 /* Parity enable */ -#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */ -#define SCI_SCXDR_MK 0x00ff /* Data register mask */ +#define SCI_RDRF 0x0040 /* Receive data register full */ +#define SCI_PE 0x0400 /* Parity enable */ +#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */ +#define SCI_SCXDR_MK 0x00ff /* Data register mask */ #define SCI_M_11 0x0200 /* Frame size is 11 bit */ #define SCI_M_10 0x0000 /* Frame size is 10 bit */ -#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */ +#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */ #define SCI_PORT_2 ((int)2) #endif /* __MPC5XX_H__ */