X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fgdsys_fpga.h;h=6d38a83d90342023d0a47bdd7e383b250f2f312f;hb=b34f8b5de0fea945c2683e9e64d941c121aa02ad;hp=0a8268cbb581ec060a6ab7f5af578488d4129429;hpb=326ea986ac150acdc7656d57fca647db80b50158;p=oweals%2Fu-boot.git diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index 0a8268cbb5..6d38a83d90 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -1,13 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ #ifndef __GDSYS_FPGA_H #define __GDSYS_FPGA_H +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS int init_func_fpga(void); enum { @@ -17,7 +17,24 @@ enum { }; int get_fpga_state(unsigned dev); -void print_fpga_state(unsigned dev); + +int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data); +int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data); + +extern struct ihs_fpga *fpga_ptr[]; + +#define FPGA_SET_REG(ix, fld, val) \ + fpga_set_reg((ix), \ + &fpga_ptr[ix]->fld, \ + offsetof(struct ihs_fpga, fld), \ + val) + +#define FPGA_GET_REG(ix, fld, val) \ + fpga_get_reg((ix), \ + &fpga_ptr[ix]->fld, \ + offsetof(struct ihs_fpga, fld), \ + val) +#endif struct ihs_gpio { u16 read; @@ -26,10 +43,12 @@ struct ihs_gpio { }; struct ihs_i2c { - u16 write_mailbox; + u16 interrupt_status; + u16 interrupt_enable; u16 write_mailbox_ext; - u16 read_mailbox; + u16 write_mailbox; u16 read_mailbox_ext; + u16 read_mailbox; }; struct ihs_osd { @@ -42,6 +61,22 @@ struct ihs_osd { u16 y_pos; }; +struct ihs_mdio { + u16 control; + u16 address_data; + u16 rx_data; +}; + +struct ihs_io_ep { + u16 transmit_data; + u16 rx_tx_control; + u16 receive_data; + u16 rx_tx_status; + u16 reserved; + u16 device_address; + u16 target_address; +}; + #ifdef CONFIG_NEO struct ihs_fpga { u16 reflection_low; /* 0x0000 */ @@ -53,75 +88,112 @@ struct ihs_fpga { }; #endif -#ifdef CONFIG_IO +#if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP) struct ihs_fpga { u16 reflection_low; /* 0x0000 */ u16 versions; /* 0x0002 */ - u16 fpga_features; /* 0x0004 */ - u16 fpga_version; /* 0x0006 */ - u16 reserved_0[5]; /* 0x0008 */ - u16 quad_serdes_reset; /* 0x0012 */ - u16 reserved_1[8181]; /* 0x0014 */ - u16 reflection_high; /* 0x3ffe */ -}; + u16 fpga_version; /* 0x0004 */ + u16 fpga_features; /* 0x0006 */ + u16 reserved_0[1]; /* 0x0008 */ + u16 top_interrupt; /* 0x000a */ + u16 reserved_1[2]; /* 0x000c */ + u16 control; /* 0x0010 */ + u16 extended_control; /* 0x0012 */ + struct ihs_gpio gpio; /* 0x0014 */ + u16 mpc3w_control; /* 0x001a */ + u16 reserved_2[2]; /* 0x001c */ + struct ihs_io_ep ep; /* 0x0020 */ + u16 reserved_3[9]; /* 0x002e */ + struct ihs_i2c i2c0; /* 0x0040 */ + u16 reserved_4[10]; /* 0x004c */ + u16 mc_int; /* 0x0060 */ + u16 mc_int_en; /* 0x0062 */ + u16 mc_status; /* 0x0064 */ + u16 mc_control; /* 0x0066 */ + u16 mc_tx_data; /* 0x0068 */ + u16 mc_tx_address; /* 0x006a */ + u16 mc_tx_cmd; /* 0x006c */ + u16 mc_res; /* 0x006e */ + u16 mc_rx_cmd_status; /* 0x0070 */ + u16 mc_rx_data; /* 0x0072 */ + u16 reserved_5[69]; /* 0x0074 */ + u16 reflection_high; /* 0x00fe */ + struct ihs_osd osd0; /* 0x0100 */ +#ifdef CONFIG_SYS_OSD_DH + u16 reserved_6[57]; /* 0x010e */ + struct ihs_osd osd1; /* 0x0180 */ + u16 reserved_7[9]; /* 0x018e */ + struct ihs_i2c i2c1; /* 0x01a0 */ + u16 reserved_8[1834]; /* 0x01ac */ + u16 videomem0[2048]; /* 0x1000 */ + u16 videomem1[2048]; /* 0x2000 */ +#else + u16 reserved_6[889]; /* 0x010e */ + u16 videomem0[2048]; /* 0x0800 */ #endif - -#ifdef CONFIG_IO64 -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_features; /* 0x0004 */ - u16 fpga_version; /* 0x0006 */ - u16 reserved_0[5]; /* 0x0008 */ - u16 quad_serdes_reset; /* 0x0012 */ - u16 reserved_1[502]; /* 0x0014 */ - u16 ch0_status_int; /* 0x0400 */ - u16 ch0_config_int; /* 0x0402 */ - u16 reserved_2[126]; /* 0x0404 */ - u16 ch0_hicb_status_int;/* 0x0500 */ - u16 ch0_hicb_config_int;/* 0x0502 */ - u16 reserved_3[7549]; /* 0x0504 */ - u16 reflection_high; /* 0x3ffe */ }; #endif -#ifdef CONFIG_IOCON +#ifdef CONFIG_STRIDER_CPU struct ihs_fpga { u16 reflection_low; /* 0x0000 */ u16 versions; /* 0x0002 */ u16 fpga_version; /* 0x0004 */ u16 fpga_features; /* 0x0006 */ - u16 reserved_0[6]; /* 0x0008 */ + u16 reserved_0[1]; /* 0x0008 */ + u16 top_interrupt; /* 0x000a */ + u16 reserved_1[3]; /* 0x000c */ + u16 extended_control; /* 0x0012 */ struct ihs_gpio gpio; /* 0x0014 */ u16 mpc3w_control; /* 0x001a */ - u16 reserved_1[19]; /* 0x001c */ - u16 videocontrol; /* 0x0042 */ - u16 reserved_2[93]; /* 0x0044 */ - u16 reflection_high; /* 0x00fe */ - struct ihs_osd osd; /* 0x0100 */ - u16 reserved_3[889]; /* 0x010e */ - u16 videomem; /* 0x0800 */ + u16 reserved_2[2]; /* 0x001c */ + struct ihs_io_ep ep; /* 0x0020 */ + u16 reserved_3[9]; /* 0x002e */ + u16 mc_int; /* 0x0040 */ + u16 mc_int_en; /* 0x0042 */ + u16 mc_status; /* 0x0044 */ + u16 mc_control; /* 0x0046 */ + u16 mc_tx_data; /* 0x0048 */ + u16 mc_tx_address; /* 0x004a */ + u16 mc_tx_cmd; /* 0x004c */ + u16 mc_res; /* 0x004e */ + u16 mc_rx_cmd_status; /* 0x0050 */ + u16 mc_rx_data; /* 0x0052 */ + u16 reserved_4[62]; /* 0x0054 */ + struct ihs_i2c i2c0; /* 0x00d0 */ }; #endif -#ifdef CONFIG_DLVISION_10G +#ifdef CONFIG_STRIDER_CON struct ihs_fpga { u16 reflection_low; /* 0x0000 */ u16 versions; /* 0x0002 */ u16 fpga_version; /* 0x0004 */ u16 fpga_features; /* 0x0006 */ - u16 reserved_0[10]; /* 0x0008 */ - u16 extended_interrupt; /* 0x001c */ - u16 reserved_1[9]; /* 0x001e */ - struct ihs_i2c i2c; /* 0x0030 */ - u16 reserved_2[16]; /* 0x0038 */ - u16 mpc3w_control; /* 0x0058 */ - u16 reserved_3[34]; /* 0x005a */ - u16 videocontrol; /* 0x009e */ - u16 reserved_4[176]; /* 0x00a0 */ - struct ihs_osd osd; /* 0x0200 */ - u16 reserved_5[761]; /* 0x020e */ - u16 videomem; /* 0x0800 */ + u16 reserved_0[1]; /* 0x0008 */ + u16 top_interrupt; /* 0x000a */ + u16 reserved_1[4]; /* 0x000c */ + struct ihs_gpio gpio; /* 0x0014 */ + u16 mpc3w_control; /* 0x001a */ + u16 reserved_2[2]; /* 0x001c */ + struct ihs_io_ep ep; /* 0x0020 */ + u16 reserved_3[9]; /* 0x002e */ + struct ihs_i2c i2c0; /* 0x0040 */ + u16 reserved_4[10]; /* 0x004c */ + u16 mc_int; /* 0x0060 */ + u16 mc_int_en; /* 0x0062 */ + u16 mc_status; /* 0x0064 */ + u16 mc_control; /* 0x0066 */ + u16 mc_tx_data; /* 0x0068 */ + u16 mc_tx_address; /* 0x006a */ + u16 mc_tx_cmd; /* 0x006c */ + u16 mc_res; /* 0x006e */ + u16 mc_rx_cmd_status; /* 0x0070 */ + u16 mc_rx_data; /* 0x0072 */ + u16 reserved_5[70]; /* 0x0074 */ + struct ihs_osd osd0; /* 0x0100 */ + u16 reserved_6[889]; /* 0x010e */ + u16 videomem0[2048]; /* 0x0800 */ }; #endif