X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Ffsl_mmdc.h;h=05fb41f40335ff29d4e6364379bce6c3a88ac9fb;hb=915f15ac5746739da0aa2ee2840c2d00dc65aaaa;hp=a939d89d6bc0d3436d126f13d53b5951a081b370;hpb=37eac3f4609c4a6b7c8c3a2f4046fbc5deb07299;p=oweals%2Fu-boot.git

diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
index a939d89d6b..05fb41f403 100644
--- a/include/fsl_mmdc.h
+++ b/include/fsl_mmdc.h
@@ -1,69 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef FSL_MMDC_H
 #define FSL_MMDC_H
 
-#define CONFIG_SYS_MMDC_CORE_ODT_TIMING		0x12554000
-#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0	0xbabf7954
-#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1	0xff328f64
-#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2	0x01ff00db
-
-#define CONFIG_SYS_MMDC_CORE_MISC		0x00001680
-#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT	0x00000800
-#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY	0x00002000
-#define CONFIG_SYS_MMDC_PHY_ODT_CTRL		0x0000022a
-
-#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY	0x00bf1023
-
-#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION	0x0000007f
-
-#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL		0xa1390003
-
-#define	FORCE_ZQ_AUTO_CALIBRATION		(0x1 << 16)
-
-/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
-#define WR_LVL_HW_EN				0x00000001
+/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
+#define MPWLGCR_HW_WL_EN		(1 << 0)
 
 /* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
-#define MPR_COMPARE_EN				0x00000001
+#define MPPDCMPR2_MPR_COMPARE_EN	(1 << 0)
 
-#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG	0x40404040
 
 /* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
-#define AUTO_RD_DQS_GATING_CALIBRATION_EN	0x10000000
+#define AUTO_RD_DQS_GATING_CALIBRATION_EN	(1 << 28)
 
 /* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
-#define AUTO_RD_CALIBRATION_EN			0x00000010
-
-#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL	0x00030035
+#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN	(1 << 4)
 
-#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT	0x00001067
+/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
+#define MMDC_MAPSR_PWR_SAV_CTRL_STAT	0x00001067
 
-#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL	0x0f3c8000
-
-#define START_REFRESH				0x00000001
+/* MMDC Core Refresh Control Register (MMDC_MDREF) */
+#define MDREF_START_REFRESH	(1 << 0)
 
 /* MMDC Core Special Command Register (MDSCR) */
-#define CMD_ADDR_MSB_MR_OP(x)   (x << 24)
-
-#define  CMD_ADDR_LSB_MR_ADDR(x)    (x << 16)
-
-#define DISABLE_CFG_REQ		0x0
-#define CONFIGURATION_REQ	(0x1  << 15)
-#define WL_EN			(0x1  << 9)
-
-#define	CMD_NORMAL		(0x0 << 4)
-#define	CMD_PRECHARGE		(0x1 << 4)
-#define	CMD_AUTO_REFRESH	(0x2 << 4)
-#define	CMD_LOAD_MODE_REG	(0x3 << 4)
-#define	CMD_ZQ_CALIBRATION	(0x4 << 4)
-#define	CMD_PRECHARGE_BANK_OPEN	(0x5 << 4)
-#define	CMD_MRR			(0x6 << 4)
-
+#define CMD_ADDR_MSB_MR_OP(x)	(x << 24)
+#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
+#define MDSCR_DISABLE_CFG_REQ   (0 << 15)
+#define MDSCR_ENABLE_CON_REQ	(1 << 15)
+#define MDSCR_CON_ACK		(1 << 14)
+#define MDSCR_WL_EN		(1 << 9)
+#define	CMD_NORMAL		(0 << 4)
+#define	CMD_PRECHARGE		(1 << 4)
+#define	CMD_AUTO_REFRESH	(2 << 4)
+#define	CMD_LOAD_MODE_REG	(3 << 4)
+#define	CMD_ZQ_CALIBRATION	(4 << 4)
+#define	CMD_PRECHARGE_BANK_OPEN	(5 << 4)
+#define	CMD_MRR			(6 << 4)
 #define CMD_BANK_ADDR_0		0x0
 #define CMD_BANK_ADDR_1		0x1
 #define CMD_BANK_ADDR_2		0x2
@@ -73,8 +48,22 @@
 #define CMD_BANK_ADDR_6		0x6
 #define CMD_BANK_ADDR_7		0x7
 
+/* MMDC Core Control Register (MDCTL) */
+#define MDCTL_SDE0		(1 << 31)
+#define MDCTL_SDE1		(1 << 30)
+
+/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
+#define MPZQHWCTRL_ZQ_HW_FORCE	(1 << 16)
+
+/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
+#define MMDC_MPMUR0_FRC_MSR	(1 << 11)
+
+/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
+/* default 64 for a quarter cycle delay */
+#define MMDC_MPRDDLCTL_DEFAULT_DELAY	0x40404040
+
 /* MMDC Registers */
-struct mmdc_p_regs {
+struct mmdc_regs {
 	u32 mdctl;
 	u32 mdpdc;
 	u32 mdotc;
@@ -120,7 +109,10 @@ struct mmdc_p_regs {
 	u32 mprddqby1dl;
 	u32 mprddqby2dl;
 	u32 mprddqby3dl;
-	u32 res5[4];
+	u32 mpwrdqby0dl;
+	u32 mpwrdqby1dl;
+	u32 mpwrdqby2dl;
+	u32 mpwrdqby3dl;
 	u32 mpdgctrl0;
 	u32 mpdgctrl1;
 	u32 mpdgdlst0;
@@ -157,4 +149,23 @@ struct mmdc_p_regs {
 	u32 mpdccr;
 };
 
+struct fsl_mmdc_info {
+	u32 mdctl;
+	u32 mdpdc;
+	u32 mdotc;
+	u32 mdcfg0;
+	u32 mdcfg1;
+	u32 mdcfg2;
+	u32 mdmisc;
+	u32 mdref;
+	u32 mdrwd;
+	u32 mdor;
+	u32 mdasp;
+	u32 mpodtctrl;
+	u32 mpzqhwctrl;
+	u32 mprddlctl;
+};
+
+void mmdc_init(const struct fsl_mmdc_info *);
+
 #endif /* FSL_MMDC_H */