X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Ffsl_esdhc.h;h=e15d3aeaec5e8b48a926fb6e080f4f0fee3e072d;hb=a4562d0640264eac8ebca544be777ed125b260d7;hp=313fa1e312a89adea20a488f00a3b756a25edcf6;hpb=57c6941b433722ab83a50dab35b8ab5a0954942a;p=oweals%2Fu-boot.git diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 313fa1e312..e15d3aeaec 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -10,25 +10,37 @@ #ifndef __FSL_ESDHC_H__ #define __FSL_ESDHC_H__ -#include +#include #include /* needed for the mmc_cfg definition */ #include +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT +#include "../board/freescale/common/qixis.h" +#endif + /* FSL eSDHC-specific constants */ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 #define SYSCTL_CLOCK_MASK 0x0000fff0 +#if !defined(CONFIG_FSL_USDHC) #define SYSCTL_CKEN 0x00000008 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 +#endif #define SYSCTL_RSTA 0x01000000 #define SYSCTL_RSTC 0x02000000 #define SYSCTL_RSTD 0x04000000 +#define VENDORSPEC_CKEN 0x00004000 +#define VENDORSPEC_PEREN 0x00002000 +#define VENDORSPEC_HCKEN 0x00001000 +#define VENDORSPEC_IPGEN 0x00000800 +#define VENDORSPEC_INIT 0x20007809 + #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) #define IRQSTAT_AC12E (0x01000000) @@ -74,6 +86,9 @@ #define IRQSTATEN_TC (0x00000002) #define IRQSTATEN_CC (0x00000001) +#define ESDHCCTL 0x0002e40c +#define ESDHCCTL_PCS (0x00080000) + #define PRSSTAT 0x0002e024 #define PRSSTAT_DAT0 (0x01000000) #define PRSSTAT_CLSL (0x00800000) @@ -82,6 +97,7 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_SDSTB (0X00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) #define PRSSTAT_CIDHB (0x00000001) @@ -155,10 +171,13 @@ #define ESDHC_HOSTCAPBLT_DMAS 0x00400000 #define ESDHC_HOSTCAPBLT_HSS 0x00200000 +#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */ + struct fsl_esdhc_cfg { - u32 esdhc_base; + phys_addr_t esdhc_base; u32 sdhc_clk; u8 max_bus_width; + u8 wp_enable; struct mmc_config cfg; };