X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Ffsl_ddr_sdram.h;h=b8de46bb42e8ec4e0d1af604fcdcfe909341dbb2;hb=27326c7ee269ff351bba8c2461e19f29d66b6a3a;hp=44ae7fbb9cede2a17c90a95499c29e0bf6df9517;hpb=074596c0b5f4e9a3642a3159a9fc7f8b8064c18a;p=oweals%2Fu-boot.git

diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 44ae7fbb9c..b8de46bb42 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -173,6 +173,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 
 /* DDR_CDR1 */
 #define DDR_CDR1_DHC_EN	0x80000000
+#define DDR_CDR1_V0PT9_EN	0x40000000
 #define DDR_CDR1_ODT_SHIFT	17
 #define DDR_CDR1_ODT_MASK	0x6
 #define DDR_CDR2_ODT_MASK	0x1
@@ -189,6 +190,13 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_MR5_CA_PARITY_LAT_4_CLK	0x1 /* for DDR4-1600/1866/2133 */
 #define DDR_MR5_CA_PARITY_LAT_5_CLK	0x2 /* for DDR4-2400 */
 
+/* DEBUG_26 register */
+#define DDR_CAS_TO_PRE_SUB_MASK  0x0000f000 /* CAS to preamble subtract value */
+#define DDR_CAS_TO_PRE_SUB_SHIFT 12
+
+/* DEBUG_29 register */
+#define DDR_TX_BD_DIS	(1 << 10) /* Transmit Bit Deskew Disable */
+
 
 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
 	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
@@ -292,7 +300,7 @@ typedef struct fsl_ddr_cfg_regs_s {
 	unsigned int ddr_cdr2;
 	unsigned int err_disable;
 	unsigned int err_int_en;
-	unsigned int debug[32];
+	unsigned int debug[64];
 } fsl_ddr_cfg_regs_t;
 
 typedef struct memctl_options_partial_s {
@@ -367,7 +375,8 @@ typedef struct memctl_options_s {
 	unsigned int additive_latency_override_value;
 
 	unsigned int clk_adjust;		/* */
-	unsigned int cpo_override;
+	unsigned int cpo_override;		/* override timing_cfg_2[CPO]*/
+	unsigned int cpo_sample;		/* optimize debug_29[24:31] */
 	unsigned int write_data_delay;		/* DQS adjust */
 
 	unsigned int cswl_override;