X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Ffsl_ddr_sdram.h;h=56c9db2594c07b6c2ddca8bafc4f993a9e0ab3d7;hb=f12f96cfaf53d47aa58eb640744542446aac44dd;hp=6a1f04b81ac400485c9f401ebba050e78502e922;hpb=c1a16c3ab541c014b029b42cc27cae496107e170;p=oweals%2Fu-boot.git

diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 6a1f04b81a..56c9db2594 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -1,7 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright 2008-2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0
+ * Copyright 2008-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP Semiconductor
  */
 
 #ifndef FSL_DDR_MEMCTL_H
@@ -366,6 +366,7 @@ typedef struct memctl_options_s {
 	unsigned int quad_rank_present;
 	unsigned int ap_en;	/* address parity enable for RDIMM/DDR4-UDIMM */
 	unsigned int x4_en;	/* enable x4 devices */
+	unsigned int package_3ds;
 
 	/* Global Timing Parameters */
 	unsigned int cas_latency_override;
@@ -408,6 +409,7 @@ typedef struct memctl_options_s {
 	unsigned int rcw_override;
 	unsigned int rcw_1;
 	unsigned int rcw_2;
+	unsigned int rcw_3;
 	/* control register 1 */
 	unsigned int ddr_cdr1;
 	unsigned int ddr_cdr2;