X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2Ftrizepsiv.h;h=2512f93f9c682940462f37b61f94903a2eff27be;hb=52eb2c79110151b9017a0829c4d44ee7b8e2ca04;hp=0a8e9941232cd75dbe8eb3374e9f61ae38913a1e;hpb=ee924e00300bd1136589b2d5f8ad1f008df01bd4;p=oweals%2Fu-boot.git

diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index 0a8e994123..2512f93f9c 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -44,16 +44,19 @@
 
 #define CONFIG_MMC		1
 #define BOARD_LATE_INIT		1
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_NO_DCACHE
+
 #define RTC
 
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -62,6 +65,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_SERIAL_MULTI
 #define CONFIG_FFUART	       1       /* we use FFUART on Conxs */
 #define CONFIG_BTUART	       1       /* we use BTUART on Conxs */
@@ -79,7 +83,6 @@
  */
 #include <config_cmd_default.h>
 
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_IMLS
 #define CONFIG_CMD_PING
@@ -164,17 +167,19 @@
 #define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
 #define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
 #define CONFIG_SYS_LOAD_ADDR		0xa1000000	/* default load address */
 
-#define CONFIG_SYS_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CPUSPEED		0x207		/* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
 
 						/* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
+#ifdef CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_CMD_MMC
 #define CONFIG_SYS_MMC_BASE		0xF0000000
+#endif
 
 /*
  * Stack sizes
@@ -207,6 +212,9 @@
 
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * GPIO settings
  */
@@ -234,11 +242,17 @@
 #define CONFIG_SYS_GRER1_VAL		0x00000000
 #define CONFIG_SYS_GRER2_VAL		0x00000000
 #define CONFIG_SYS_GRER3_VAL		0x00000000
-#define CONFIG_SYS_GFER0_VAL		0x00000000
+
 #define CONFIG_SYS_GFER1_VAL		0x00000000
-#define CONFIG_SYS_GFER2_VAL		0x00000000
 #define CONFIG_SYS_GFER3_VAL		0x00000020
 
+#if CONFIG_POLARIS
+#define CONFIG_SYS_GFER0_VAL		0x00000001
+#define CONFIG_SYS_GFER2_VAL		0x00200000
+#else
+#define CONFIG_SYS_GFER0_VAL		0x00000000
+#define CONFIG_SYS_GFER2_VAL		0x00000000
+#endif
 
 #define CONFIG_SYS_PSSR_VAL		0x20	/* CHECK */
 
@@ -254,7 +268,11 @@
 
 #define CONFIG_SYS_MSC0_VAL		0x4df84df0
 #define CONFIG_SYS_MSC1_VAL		0x7ff87ff4
+#if CONFIG_POLARIS
+#define CONFIG_SYS_MSC2_VAL		0xa2697ff8
+#else
 #define CONFIG_SYS_MSC2_VAL		0xa26936d4
+#endif
 #define CONFIG_SYS_MDCNFG_VAL		0x880009C9
 #define CONFIG_SYS_MDREFR_VAL		0x20ca201e
 #define CONFIG_SYS_MDMRS_VAL		0x00220022
@@ -273,8 +291,15 @@
 #define CONFIG_SYS_MCIO0_VAL		0x00008407
 #define CONFIG_SYS_MCIO1_VAL		0x0000c108
 
+#define CONFIG_NET_MULTI		1
 #define CONFIG_DRIVER_DM9000		1
-#define CONFIG_DM9000_BASE	0x08000000
+
+#if CONFIG_POLARIS
+#define CONFIG_DM9000_BASE		0x0C800000
+#else
+#define CONFIG_DM9000_BASE		0x08000000
+#endif
+
 #define DM9000_IO			CONFIG_DM9000_BASE
 #define DM9000_DATA			(CONFIG_DM9000_BASE+0x8004)
 
@@ -306,6 +331,9 @@
 /* write flash less slowly */
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
 
+/* Unlock to be used with Intel chips */
+#define CONFIG_SYS_FLASH_PROTECTION	1
+
 /* Flash environment locations */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector	*/